	SUBTTL	DOUBLE D SYSTEM CONFIGURATION DEFINITIONS
;****************************************************************************
;
;	THIS INCLUDE MODULE DEFINES THE SYSTEM TO BOARD LEVEL PARAMETERS FOR
;  THE JADE DOUBLE D DISK CONTROLLER. IT SHOULD BE INCLUDED AS DEFINITIONS
;  WHENEVER THE BOARD IS DIRECTLY INTERFACED TO BY A SOFTWARE MODULE.
;
;****************************************************************************
;
;	REVISIONS:
;  1.0	19 JUL 82
;	RELEASE
;
;  1.1	14 FEB 83
;	CHANGED TO REFLECT REV C BOARD HARDWARE CHANGES:
;	  MA10 IN STATUS PORT BIT 1 & DELETION OF MEMORY ACKNOWLEDGE BIT 0
;	  IN STATUS PORT & MOVE OF HALT FLAG FROM BIT 1 TO BIT 0 OF STATUS
;	  PORT.
; 1.2 -	23 OCT 83   GRH
;	CLEANED UP, ADDED HEADER GRAPHICS
;
; 1.3 - 7 JUN 85   GRH
;	Added Jade format disk descriptor sector definitions.
;
; 1.4 -	29 OCT 85   GRH
;	Changed disk descriptor sector format to new format.
;	Clarified communication block commands.
;	Added hook for log-on return of valid disk descriptor boolean.
;	Removed disk format data & command block data definitions to JDDDISK
;
; 2.0 - 24 NOV 85   GRH
;	Rework for prom code.
;	Change command block structure to reflect Common IOPB structure.
;
; 2.1 -	22 FEB 86   GRH
;	Removed command block definitions to a separate file ('COMIOPB.DEF').
;	Removed duplicate definitions.
;
;****************************************************************************


;============================================================================
;
;				LOCATIONS
;
;============================================================================
DDBASE	EQU	0E000H		;DD WINDOW BASE ADDR (ADDED TO STATUS BITS)
DDFBFO	EQU	00H		;DD FORMAT BUFFER OFFSET (BANK 1)
DDPORT3	EQU	41H		;3" DRIVE CONTROLLER
DDPORT5	EQU	42H		;5 1/4" DRIVE CONTROLLER
DDPORT8	EQU	43H		;8" DRIVE CONTROLLER
DDCBO	EQU	370H		;DCM COMMAND BLOCK OFFSET


;============================================================================
;
;			DOUBLE D COMMAND PORT
;
;============================================================================
;
;	 D7			      D0
;	|BGN| X | X | X | X | X |MB1|MB0|
;	  ^			 \______/
;	  |			    |_______ 00: REMOVE MEMORY BANK FROM HOST
;	  |				     01: SELECT 1K MEMORY BANK 0
;	  |				     10: GENERATE PROCESSOR INTERRUPT
;	  |			  	     11: SELECT 1K MEMORY BANK 1
;	  |_________________________________ RESET BOARD PROCESSOR (1)
;
;
;   COMMANDS (OUTPUT TO DDPORT)
;
DDBGN	EQU	10000000B	;RESET DD Z80A
DDFREE	EQU	00000000B	;RELEASE MEMORY WINDOW (CPU FREE RUN)
DDMB0	EQU	00000001B	;SELECT MEMORY BANK 0
DDMB1	EQU	00000011B	;SELECT MEMORY BANK 1
DDEXC	EQU	00000010B	;ISSUE DD INTERRUPT (EXECUTE COMMAND BLOCK)


;============================================================================
;
;		STATUS PORT (SAME ADDRESS AS DDPORT)
;
;============================================================================
;
;	 D7			      D0
;	| X | X | X | 0 |S12|S11|S10|HLT|
;		      ^	 \_________/  ^_____ PROCESSOR HALT FLAG (0)
;		      |	      |_____________ BOARD MEMORY ADDR SWITCH POS.
;		      |_____________________ BOARD ACKNOWLEDGE (ALLWAYS 0)
;
DDSHLT	EQU	00000001B	;STATUS PORT HALT FLAG, 0= HALT, 1= BUSY
DDSASW	EQU	00001110B	;STATUS PORT ADDR SW MASK
DDSACK	EQU	00010000B
;
;	END	FILE
