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00:39:18 <cbridge_> <veltas> Programming war crimes
00:39:51 <cbridge_> <veltas> 
ACTION chuckles

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03:23:19 <cbridge_> <eris[m]1> <siraben "eris: a war criminal because you"> yes
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11:45:16 <cbridge_> <Zarutian_HTC> re logisim evolution: the 3.5.0 version does not have a dual ported RAM component
11:46:59 <cbridge_> <Zarutian_HTC> dual ported basically means that the component has two sets of address and data lines independent of each other but give access to the same memory cells 
11:48:22 <cbridge_> <Zarutian_HTC> did not a big one so I made one as sub circuit that uses registers. One per memory cell
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16:26:59 <cbridge_> <dave0> maw
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20:05:31 <cbridge_> <dave0> re maw
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