00:00:00 --- log: started forth/20.01.17 00:06:18 --- join: djinni joined #forth 00:35:52 --- quit: WickedShell (Remote host closed the connection) 00:38:01 --- join: mtsd joined #forth 01:21:48 --- join: xek joined #forth 01:24:37 --- join: dys joined #forth 02:29:40 --- join: dddddd joined #forth 02:51:51 --- quit: mtsd (Quit: Leaving) 02:54:33 --- quit: smokeink (Ping timeout: 272 seconds) 03:07:00 --- nick: jedb_ -> jedb 03:13:41 --- join: iyzsong joined #forth 03:45:01 proteusguy: no, not at the moment. My next step toward forth is a RPN assembler (basically forth but a word for each instruction), later on I'd like to make a foth and then build other languages on top of it as parsing words 03:45:01 --- join: Labu joined #forth 03:45:58 --- quit: rdrop-exit (Quit: Lost terminal) 03:58:37 --- join: iyzsong-x joined #forth 03:59:29 --- quit: iyzsong (Ping timeout: 265 seconds) 04:50:23 --- join: smokeink joined #forth 04:57:30 --- join: MrMobius joined #forth 04:57:48 --- quit: iyzsong-x (Quit: ZNC 1.7.1 - https://znc.in) 04:58:14 --- quit: jedb (Remote host closed the connection) 04:58:27 --- join: jedb joined #forth 05:18:14 --- join: proteus-guy joined #forth 06:12:40 --- quit: smokeink (Ping timeout: 268 seconds) 06:19:38 --- quit: proteus-guy (Ping timeout: 268 seconds) 06:20:19 --- join: proteus-guy joined #forth 06:37:19 --- quit: proteus-guy (Ping timeout: 268 seconds) 06:38:20 --- quit: dave0 (Quit: dave's not here) 06:56:29 --- quit: jsoft (Ping timeout: 272 seconds) 07:01:37 --- quit: X-Scale (Ping timeout: 240 seconds) 07:02:40 --- join: X-Scale` joined #forth 07:03:38 --- nick: X-Scale` -> X-Scale 08:48:33 --- quit: crab1 (Ping timeout: 258 seconds) 09:00:40 --- quit: dys (Ping timeout: 245 seconds) 10:25:18 --- join: dys joined #forth 10:25:36 Typed stack effects, cool. Food for thought... 10:28:48 halting problem? 10:31:03 (or a relative to it, maybe) 10:41:03 --- join: proteus-guy joined #forth 11:16:57 --- quit: reepca (Remote host closed the connection) 11:17:10 --- join: reepca joined #forth 11:17:29 --- quit: dys (Ping timeout: 268 seconds) 11:47:44 --- join: Tony_Sidaway joined #forth 11:51:07 Seem to have fallen into an analogue synth (well...hybrid I suppose) rabbit hole. I'm building a nice DIY synth into a second hand bookcase. Lots of modern analogue kit uses microcontrollers, so it's going to be fun to play with. Forth will be handy. 11:53:27 Modular synth field is clogged with buyers who seem to have more money than sense. I shall treat this as a challenge. The electronics involved here is very simple. 11:54:46 Also, Eurorack. Who on earth imagined 3.5mm jacks and tiny subminiature pots would be suitable for patching? 11:56:04 (Rewind a few weeks to when I seriously considered using solderless breadboards... mea culpa. I learn quickly.) 11:57:22 --- quit: reepca (Ping timeout: 268 seconds) 11:58:58 So I'm going with big jacks and big knobs and improvised cases. And no bloody aluminium rails. Because I'm not building for performance, and rails are unnecessary and expensive. Over-engineering for its own sake. 12:07:44 Love these guys on YouTube: Look Mum No Computer and Juanito Moore. 12:09:18 The latter actually builds a simple kickdrum module into a couple of tin cans, then reveals that the drum sound in his soundtrack was produced by the same module he built. 12:10:30 His stuff looks beautiful and it's quite unlike anything else in DIY electronics. 12:15:46 --- quit: Tony_Sidaway (Ping timeout: 260 seconds) 12:16:04 --- join: dys joined #forth 12:17:23 --- join: Tony_Sidaway joined #forth 12:17:24 --- quit: Tony_Sidaway (Client Quit) 12:48:27 --- join: jsoft joined #forth 13:22:05 --- quit: gravicappa (Ping timeout: 265 seconds) 13:34:46 --- part: inode left #forth 14:36:49 --- quit: xek (Ping timeout: 240 seconds) 15:40:37 --- join: dave0 joined #forth 15:46:16 --- join: smokeink joined #forth 15:50:31 --- join: ryke joined #forth 16:15:37 --- join: reepca joined #forth 16:21:39 --- quit: MrMobius (Ping timeout: 260 seconds) 16:22:41 --- join: MrMobius joined #forth 17:17:25 --- quit: ryke (Ping timeout: 268 seconds) 17:32:41 --- quit: Labu (Quit: Leaving.) 18:10:37 --- join: rdrop-exit joined #forth 18:12:24 bonjour Fortheurs 18:55:07 dddddd re:halting problem - it does make for challenges as to what can be determined at compile time vs runtime. Naturally you want as much as possible to be resolved at compile time. It will radically alter (guide perhaps?) your coding style - in a good way. 19:07:45 ello,ello Mr Zen Forth Guru! 19:08:03 hello proteusguy :) 19:19:11 --- quit: dddddd (Remote host closed the connection) 19:47:18 hello Forth Master Technician (tm) 19:47:26 hello proteusguy 19:51:56 --- join: iyzsong joined #forth 20:43:30 --- quit: smokeink (Remote host closed the connection) 20:43:53 --- join: gravicappa joined #forth 20:48:01 --- quit: gravicappa (Ping timeout: 240 seconds) 21:01:15 --- join: gravicappa joined #forth 21:12:19 What's going on team 21:14:08 --- quit: gravicappa (Ping timeout: 258 seconds) 21:14:15 Forth dude, what else ? 21:14:59 hi jsoft 21:20:01 rdrop-exit, I had to laugh, when I looked at the Mecrisp usart code in the GD32VF103 i saw that matthias has just dumped in all the equates from the STM32F103 usart code and just changed the isa from thumb to risc-v 21:21:00 rdrop-exit, so it seems some people arent playing the "lets change every bitfield name in gd32VF103" game 21:22:25 rdrop-exit, another interesting thing I found, the Gigadevices docs are just hopeless! Anyone who ever thought the STM docs were poor is in for a rude awakening 21:22:52 bbl 21:23:04 ok cya 21:24:19 --- join: gravicappa joined #forth 21:26:58 Luckily I've never delved into ARM, so I remain blissfully oblivious to any differences there might be between boards sporting RISC-V and similar boards sporting ARM. 21:33:39 --- quit: gravicappa (Ping timeout: 272 seconds) 21:45:00 For now my focus is on leveraging RISC-V's hardware debug infrastructure for a tethered Forth. 21:47:51 tpbsd, what is this board you are playing with, This RISC-V thing? 21:50:02 He has a page on it on his site, I'll dig up the url 21:50:38 https://mecrisp-stellaris-folkdoc.sourceforge.io/stm32f103-vs-gd32vf103.html 21:57:41 hey rdrop-exit - how's things. Just got back home from brunch & shopping with the wife. 21:59:04 rdrop-exit, I participated in some of the standards meetings for that debug infrastructure on RISCV. Can't say I contributed much but these guys were quite serious in getting it right. I'm sure they'd appreciate any feedback. 22:01:25 rdrop-exit, your board is the one with the little screen? that's cool! do you have to provide your own font data or does it come with one already? 22:02:26 Hi proteusguy, good to know thanks 22:03:03 The board on that page is what tpbsd has 22:03:16 oic - well same question to tpbsd then... ;-) 22:05:31 What is your involvement with the RISC-V standards? 22:06:54 Is your company involved with RISC-V? 22:10:27 Just personal interest. I got some of the very early SOCs and played with them a bit. Mostly glad to see a promising open standard ISA take hold given how much I loath ARM and x86 ISAs. 22:10:50 rdrop-exit, hmm 22:10:58 Cool! 22:11:18 Also chisel3 was quite interesting to me because of my desire to make a forth-ish cpu and don't want to right verilog or vhdl. 22:13:58 I see. I haven't looked at chisel3. 22:15:01 I'm ok with Verilog/SV. 22:30:32 rdrop-exit, working with a higher level language like Scala for chisel3 or python for migen or myhdl provides Soooo much better abstractions and flexibility for the fpga design. Ultimately I'd like to make my own in ActorForth (one day....). Naturally they produce verilog as their output. 22:32:14 I find SV has enough abstractions and parameterization capabilities for me, I don't really crave more. 23:16:49 --- quit: dys (Ping timeout: 240 seconds) 23:59:59 --- log: ended forth/20.01.17