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21:10:08 <tp> G'day Forthlanders, anyone working on any interesting tech ?
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21:17:54 <rdrop-exit> Hello tp!
21:18:52 <tp> g'day rdrop-exit !
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21:21:14 <rdrop-exit> source  RISC-V - XDS - DM - DMI Bus Registers - Abstract Command
21:21:14 <rdrop-exit> $ 17  constant command
21:21:14 <rdrop-exit> 31 24 bits  constant %command.cmdtype
21:21:14 <rdrop-exit> 23  0 bits  constant %command.control
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21:21:56 <rdrop-exit> (taking nots as I read)
21:23:10 <tp> is your RISC-V bursting at the debug seams ?
21:23:49 <tp> that looks like interesting hitech
21:23:53 <rdrop-exit> I downloaded the debug spec, I'm making "code" notes as I read along
21:24:00 <tp> ah
21:25:25 <tp> I always make extensive notes in my Forth sourcecode but theyre all stripped before upload so the net slowdown is 0%
21:26:13 <tp> thats the BLOCKS equivalent of my 'semi tethered' Forth ;-)
21:26:21 <rdrop-exit> :)
21:27:24 <rdrop-exit> I'm just going to interactively control the cores via JTAG and the debug spec
21:27:40 <tp> it would make the standard 9600 baud terminal upload where the on chip Forth has to read and reject comments unbearably painful tho
21:28:00 <rdrop-exit> No comments, no source
21:28:27 <rdrop-exit> The source and comments stay on the host PC
21:28:36 <tp> yes I know you are. You do have comments and source somewhere tho before the binary hits the metal
21:28:54 <rdrop-exit> Only on the host
21:29:06 <tp> yeah of course
21:29:47 <tp> I did do a test once and found that approx 17% of my source is comprised of comments
21:30:07 <rdrop-exit> With the debug interface I'll be able to halt cores, write to their registers or memory without sending any source
21:31:01 <rdrop-exit> All your cores are belong to us
21:31:03 <tp> sure, tho the binary commands you do send will hopefully be influenced by Forth source at the beginning ;-)
21:31:29 <tp> and hopefully they will a facility for all the comments you need
21:32:01 <tp> Im a monocore man myself, I have enough problems with only one core
21:33:11 <rdrop-exit> Yes, it'll be Forth words on the host that lay down object code, and also Forth words on the host that control the target and write the object code to the target's memory
21:33:31 <tp> I tend to make gear that lives in the electromechanical world, where events proceed glacially from the viewpoint of even a 8Mhz mcu
21:33:34 <rdrop-exit> (including flash)
21:34:18 <tp> sure, typical tethering, very similar to mecrisp-across (msp430)
21:34:46 <rdrop-exit> I doubt I'll do anything but monocore, but it's nice to know that their debug interface handles multi-core sceanrios
21:34:57 <rdrop-exit> * scenarios
21:36:15 <tp> altho I appreciate that your system is a self bootstrapping, homogeneous, leading edge historically based Forth, using the latest in phase locked dipthon retarding code
21:36:16 <rdrop-exit> This all assumes I'm capable of decyphering this spec and make practical use out of it
21:36:41 <rdrop-exit> (and then I still have to learn the ISA)
21:36:58 <rdrop-exit> :))
21:37:06 <tp> multicore debug will be a real noodle twister I think
21:38:42 <tp> it also assumes the spec is complete and implemented properly ... like always ;-)
21:39:02 <rdrop-exit> As usual the problem with standards is all the optional stuff
21:39:17 <tp> I know there is a ton of RISC-V specs still not complete and may not be for years
21:39:21 <tp> absolutely 
21:40:15 <rdrop-exit> I'll probably do my initial tests with a board from SiFive, since their the most active players in producing the spec
21:40:25 <tp> good plan
21:40:27 <rdrop-exit> * they're the most ...
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21:41:16 <tp> the Chinese RISC-V chips will come and go, I wouldnt put much effort into them until they have been around a decade or so
21:41:23 <rdrop-exit> I'm in no rush, I don't have a killer app/product in mind anyway
21:41:37 <tp> I think those days are gone
21:42:15 <tp> these days the only real 'killer apps' are in missile guidance
21:42:25 <rdrop-exit> shhh
21:43:09 <tp> mankind is jaded to the max now, not much surprises us anymore
21:43:31 <rdrop-exit> I'm being called for late lunch, catch you later Forth Master Technician
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21:43:46 <tp> reusable first stage rockets ?... great, whats for dinner ?
21:43:58 <tp> cya layer Zen Forth Guru
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