00:00:00 --- log: started forth/18.03.26 00:57:44 --- quit: dys (Ping timeout: 264 seconds) 00:57:46 --- join: smokeink (~smokeink@59-125-28-152.HINET-IP.hinet.net) joined #forth 01:01:48 --- join: dddddd (~dddddd@unaffiliated/dddddd) joined #forth 01:04:40 --- join: ncv (~neceve@unaffiliated/neceve) joined #forth 01:31:20 --- quit: smokeink (Quit: Leaving) 02:41:06 --- join: smokeink (~smokeink@59-125-28-152.HINET-IP.hinet.net) joined #forth 03:07:22 --- quit: dddddd (Read error: Connection reset by peer) 03:09:29 --- join: proteusguy (~proteus-g@122.147.252.210) joined #forth 03:09:29 --- mode: ChanServ set +v proteusguy 03:23:13 --- quit: smokeink (Remote host closed the connection) 03:36:01 --- join: smokeink (~smokeink@59-125-75-78.HINET-IP.hinet.net) joined #forth 03:45:39 --- quit: smokeink (Ping timeout: 268 seconds) 04:33:33 --- quit: nighty- (Quit: Disappears in a puff of smoke) 05:40:51 --- join: smokeink (~smokeink@59-125-28-152.HINET-IP.hinet.net) joined #forth 05:45:17 --- join: dddddd (~dddddd@unaffiliated/dddddd) joined #forth 07:15:03 --- join: nighty- (~nighty@s229123.ppp.asahi-net.or.jp) joined #forth 07:39:39 --- join: Gromboli (~Gromboli@static-72-88-80-103.bflony.fios.verizon.net) joined #forth 08:24:39 --- quit: smokeink (Remote host closed the connection) 08:25:03 --- join: smokeink (~smokeink@59-125-28-152.HINET-IP.hinet.net) joined #forth 08:57:21 --- quit: smokeink (Remote host closed the connection) 09:01:59 --- quit: Labu (Ping timeout: 248 seconds) 09:21:35 --- join: Labu (~mik@mvice.pck.nerim.net) joined #forth 09:44:09 --- join: Mat4 (~yaaic@ip5b409e5e.dynamic.kabel-deutschland.de) joined #forth 09:47:11 G'Day, is someone here interested in dynamic FPGA reconfiguration instead of compilation for Forth ? 09:58:05 --- quit: ncv (Ping timeout: 246 seconds) 09:59:46 Mat4: sure, I have found dynamic FPGA (partial) reconfiguration a rather nifty feature. 10:20:46 I think about combining the FPGA with a Propeller chip and writing a Forth for it which generate bitstreams 10:23:20 sadly the required time for reconfiguration can be still high 10:25:58 yeah, I never understood why bitstream ?sections/areas? are often so big on many FPGAs 10:28:15 so my idea is configure the FPGA with a FPGA alike softcore. Because the logic 10:29:34 configuRation now does not change this bottleneck is compensated 10:30:36 at least theoretical. What do Dou think about it ? 10:31:04 one thing I have noticed is that most FPGAs, I have looked the datasheets for, are clocked while many CPLDs are completely async. 10:32:43 oh, to my knowledge There exist some expensive FPGA with async blocks 10:34:13 the most basic FPGAs are as I understand it a bunch of LUTs within a configurable routing fabric 10:34:44 sure many FPGAs have hard special blocks in them nowdays due to the cost of config sram. 10:35:12 Probably a little CPLD array would be an alternative 10:35:53 but why does all those LUTs have to be clocked? Sure you have to deal with designing around glitches 10:37:27 CPLD arrays are as I understand them mostly macrocells with configurable routing network but where the config memory is flash, mram, fram or other nvram based cells. 10:38:01 (CPLDs are often used where you dont have time to do startup config like with FPGAs) 10:39:36 Mat4, Zarutian_PI: That's what I'm doing with the Cypress PSoC 5LP. Dynamic reconfiguration of its digital logic fabric (the UDB array/CPLD) and analog fabric (the UAB array/FPAA). Compiling Forth to the PSoC's logic fabric with lazy evaluation. 10:41:23 FPGA's seem to require probably clock synchronisation because of timing issues configuring different Logic blocks 10:42:34 Mat4: I do not mind the SPI like clocking in the config cell contents but why cant the LUTs be unclocked? 10:43:12 Zarutian_PI: The PSoC 6 traded half the 24 UDB's for SmartIO blocks. The PSoC 6 SmartIO blocks support unclocked, asynchronous configurable LUT logic. 10:44:11 (good for waking up the rest of the PSoC with logic) 10:46:07 well, damn, Cypress keeps suprising me 10:46:19 Mat4: The PSoC 6 chips are about 4 to 10 USD. Not half bad. 10:46:42 make awfully good parallel access sram chips btw. 10:47:06 pointfree: what do you think about my idea ? 10:47:18 pointfree: available in any handy FQN packages (I detest ball arrays) 10:47:26 ? 10:49:22 Mat4: reconfiguring the fgpa from the fabric itself? 10:49:36 yes 10:50:37 Mat4: This is possible in Xilinx parts with the ICAP. 10:51:40 or configurate the FPGA with a soft-core FPGA which is dynamic reprogrammable 10:52:47 Mat4: So having two fpgas reconfiguring each other? 10:54:46 Zarutian_PI: Your choices are BGA or CSP 10:54:46 http://www.cypress.com/search/psg/114026#/?_facetShow=ss_pmain_core,ss_psecondary_core,fs_pmax_operating_frequency_mhz_,fs_pflash_kb_,fs_psram_kb_,fs_pno_of_gpios,fs_pble_maximum_data_rate_mbps_,fs_pble_power_output_dbm_,fs_pble_rx_sensitivity_dbm_,fs_pble_supported_frequency_band_ghz_,ss_pdedicated_adc___max_resolution_sample_rate_,ss_pcapsense,ss_pfs_usb,ss_pdedicated_dac___max_resolution_sample_rate_,fs_pno_of_dedicated_op 10:54:46 amps,fs_pno_of_dedicated_comparators,fs_pno_of_dedicated_timer_counter_pwm_blocks,fs_pno_of_serial_communication_blocks_i2c_uart_spi_,fs_psmart_i_o,fs_pno_of_programmable_universal_digital_blocks,ss_plcd_direct_drive,ss_pcryptographics_accelerator,ss_pquad_spi,fs_pi2s,fs_pno_of_can_controllers,fs_pno_of_dma_channels,ss_field_package_type,ss_ppackage,fs_pmax_operating_temp_c_,fs_pmax_operating_voltage_v_,fs_pmin_operating_temp 10:54:46 _c_,fs_pmin_operating_voltage_v_,ss_ptape_reel 10:54:57 wow say it don't spray it 10:55:26 no, I mean something like a soft-core CPU which addresses most FPGA Ressources like an FPGA 10:55:28 pointfree: just this once, use an url shortener. 10:55:32 bad link paste buh 10:57:00 my bad 10:57:26 Zarutian_PI: There are of course some devkits 10:58:42 pointfree: dont know about those. If they sell these chips on breakout boards though then I wont mind. 11:02:20 Mat4: interesting idea! 11:17:54 Mat4: I actually don't know much about how logic fabric is reconfigured on devices besides the PSoC 5LP. The PSoC 5LP logic fabric is all memory mapped which makes it convenient for that although the ARM Cortex M3 is of course not a softcore. 11:18:02 Apparently other devices have everything on a shift register. I guess that makes it easier/possible to address huge fabrics. 11:18:24 For those devices a hilbert order would be better for partial reconfig than a boustrophedon order (better locality, hilbert space is addressed with gray code coordinates, hmm...) 11:18:36 http://people.rennes.inria.fr/Christophe.Huriaux/static/huriaux-configcomp13.pdf 11:19:15 Mat4: There is a lot to think about regarding how the fabric is configured from the (soft)core especially if that process can change with what's being configured and with what's already in the fabric. Probably fragmentation is the biggest challenge with a lot of partial live reconfig right now. 11:21:31 pointfree: can you explain a bit how gray code coordnates addressing of 2d hilbert space curve works? 11:29:53 --- join: dys (~dys@tmo-108-241.customers.d1-online.com) joined #forth 11:35:01 pointfree: agree. However it can be a method handling reconfig times (theoretical) 11:40:31 Zarutian_PI: For the first order hilbert curve view the 2 bits of the first 4 gray codes as x and y coordinates. http://blog.typeobject.com/tag/gray%20codes ... 11:40:41 Zarutian_PI: ... thereafter first order curves can be placed along a first order hilbert curve in hilbert order as well, by adding another bit on the left: the https://upload.wikimedia.org/wikipedia/commons/c/c1/Binary-reflected_Gray_code_construction.svg 11:40:45 ...so on and so forth. 11:42:04 good locality like a karnaugh map 11:49:21 --- quit: Gromboli (Quit: Leaving) 11:52:36 Mat4: I'm still trying to picture dynamic optimization of the configuration process itself. I guess you could bundle the target logic expressions (for the fpga side) and the access itself (on the softcore side) into one expression for minimization -- minimize both together. 11:54:12 --- join: Gromboli (~Gromboli@static-72-88-80-103.bflony.fios.verizon.net) joined #forth 11:56:04 pointfree: I will try it out, thanks 11:57:32 (After finishing these Systolic array CPU project) 12:15:02 --- quit: Labu (Ping timeout: 268 seconds) 12:29:42 --- join: Labu (~mik@194.242.115.78) joined #forth 13:57:21 --- quit: Labu (Ping timeout: 276 seconds) 14:17:42 --- join: wa5qjh (~quassel@freebsd/user/wa5qjh) joined #forth 14:32:50 pointfree: had to go see about dinner, eat and such. 14:33:33 pointfree: I know what graycodes are and how to make a 2d hilbert curve (I ususally go the L-system way with turtle graphics commands) 14:34:46 * Zarutian_PI edifies himself via the link pointfree gave. 14:35:25 --- join: smokeink (~smokeink@59-125-75-78.HINET-IP.hinet.net) joined #forth 14:37:04 --- quit: smokeink (Remote host closed the connection) 14:56:11 --- join: smokeink (~smokeink@185.134.120.54) joined #forth 15:08:53 --- quit: cheater (Ping timeout: 252 seconds) 15:11:25 --- join: cheater (~cheater@unaffiliated/cheater) joined #forth 15:14:47 --- quit: smokeink (Remote host closed the connection) 15:15:10 --- join: smokeink (~smokeink@li1553-99.members.linode.com) joined #forth 15:32:01 --- quit: wa5qjh (Remote host closed the connection) 15:34:14 --- join: wa5qjh (~quassel@freebsd/user/wa5qjh) joined #forth 17:03:25 --- quit: nighty- (Quit: Disappears in a puff of smoke) 17:55:39 --- join: nighty- (~nighty@kyotolabs.asahinet.com) joined #forth 18:04:57 --- quit: proteusguy (Ping timeout: 240 seconds) 18:14:09 --- quit: smokeink (Remote host closed the connection) 18:14:32 --- join: smokeink (~smokeink@59-125-75-78.HINET-IP.hinet.net) joined #forth 18:32:24 --- quit: dddddd (Read error: Connection reset by peer) 18:58:19 --- quit: cheater (Ping timeout: 264 seconds) 19:00:38 --- join: cheater (~cheater@unaffiliated/cheater) joined #forth 19:19:05 --- join: republican_devil (~g@209.6.150.53) joined #forth 19:19:09 so forth and cgi 19:19:13 anyone here doing it? 19:19:20 or web n forth of any sort? 19:22:08 --- quit: karswell (Read error: Connection reset by peer) 19:26:37 --- join: karswell (~user@cust125-dsl91-135-5.idnet.net) joined #forth 19:37:25 nope 19:37:47 i guess you need to learn some modern stacks 20:19:43 but i guess the recently FaaS became popular might let gave forth a big chance to enter web domain 20:28:13 --- quit: Gromboli (Quit: Leaving) 20:44:49 --- quit: Mat4 (Ping timeout: 276 seconds) 20:57:57 --- join: dograt (~dograt@unaffiliated/dograt) joined #forth 21:32:35 --- quit: smokeink (Remote host closed the connection) 21:32:57 --- join: smokeink (~smokeink@awork152250.netvigator.com) joined #forth 23:28:42 --- quit: dys (Ping timeout: 276 seconds) 23:59:59 --- log: ended forth/18.03.26