00:00:00 --- log: started forth/17.03.15 00:48:53 --- join: circ-user-3ReWJ (~circuser-@68.21.148.119) joined #forth 00:52:34 --- join: impomatic_ (~impomatic@host109-145-70-111.range109-145.btcentralplus.com) joined #forth 00:53:19 --- quit: impomatic (Ping timeout: 240 seconds) 00:53:29 --- nick: impomatic_ -> impomatic 01:04:23 --- quit: karswell (Read error: Connection reset by peer) 01:05:00 --- quit: circ-user-3ReWJ (Remote host closed the connection) 01:05:36 --- join: karswell (~user@158.208.208.46.dyn.plus.net) joined #forth 01:35:51 --- join: Bunny351 (~Bunny351@p4FF18F76.dip0.t-ipconnect.de) joined #forth 01:41:45 --- quit: ACE_Recliner (Ping timeout: 258 seconds) 01:45:10 --- join: John[Lisbeth] (~lisbeth@52.176.46.58) joined #forth 01:45:21 I finally put emacs to rest 01:46:30 what do you use instead? 01:50:08 --- join: mtsd (4d6e3d64@gateway/web/freenode/ip.77.110.61.100) joined #forth 01:53:08 I don't know 02:05:40 --- quit: nighty-_ (Ping timeout: 256 seconds) 02:13:05 --- join: nighty-_ (~cp@www.taiyolabs.com) joined #forth 02:19:43 --- quit: MrBusiness (Quit: https://www.youtube.com/watch?v=xIIqYqtR1lY -- Suicide is Painless - Johnny Mandel) 02:20:25 --- join: MrBusiness (~ArcMrBism@104-50-90-48.lightspeed.brhmal.sbcglobal.net) joined #forth 02:22:28 --- quit: MrBusiness (Client Quit) 02:23:05 --- join: MrBusiness (~ArcMrBism@104-50-90-48.lightspeed.brhmal.sbcglobal.net) joined #forth 02:25:28 --- quit: X-Scale (Read error: Connection reset by peer) 02:48:38 --- join: luser1 (~luser1@h69-21-248-248.crlbnm.broadband.dynamic.tds.net) joined #forth 03:59:59 --- quit: nighty- (Quit: Disappears in a puff of smoke) 04:27:49 --- quit: dys (Read error: Connection reset by peer) 05:06:05 I think maybe nano 05:06:16 Or maybe I'll make my own who knows 05:27:37 --- join: nighty (~nighty@s229123.ppp.asahi-net.or.jp) joined #forth 05:30:19 I really like joe as a simple linux text editor. 05:30:39 --- join: GeDaMo (~GeDaMo@212.225.82.133) joined #forth 05:36:57 --- quit: luser1 (Ping timeout: 240 seconds) 06:01:54 --- quit: impomatic (Quit: ChatZilla 0.9.93 [Firefox 51.0.1/20170125094131]) 06:45:36 --- part: mtsd left #forth 06:46:09 --- join: true-grue (~true-grue@176.14.222.10) joined #forth 06:52:54 --- join: Zarutian (~zarutian@168-110-22-46.fiber.hringdu.is) joined #forth 07:22:53 --- quit: Zarutian (Quit: Zarutian) 08:11:49 --- join: X-Scale (~ARM@214.20.108.93.rev.vodafone.pt) joined #forth 08:28:47 --- join: neceve (~ncv@86.125.247.109) joined #forth 08:28:47 --- quit: neceve (Changing host) 08:28:47 --- join: neceve (~ncv@unaffiliated/neceve) joined #forth 08:47:42 --- quit: wa5qjh (Remote host closed the connection) 08:58:30 --- quit: smokeink (Ping timeout: 260 seconds) 09:28:14 --- quit: midre (Ping timeout: 256 seconds) 09:28:33 --- join: midre (~midre@2601:547:500:2a80::2) joined #forth 09:41:35 --- quit: neceve (Quit: Konversation terminated!) 10:54:21 --- join: gravicappa (~gravicapp@ppp83-237-171-128.pppoe.mtu-net.ru) joined #forth 10:56:42 --- join: dys (~dys@ip-109-43-1-42.web.vodafone.de) joined #forth 11:16:55 --- quit: gravicappa (Ping timeout: 264 seconds) 11:32:37 --- join: gravicappa (~gravicapp@ppp83-237-165-148.pppoe.mtu-net.ru) joined #forth 12:48:23 --- join: impomatic (~impomatic@host109-145-70-111.range109-145.btcentralplus.com) joined #forth 12:55:39 --- join: ACE_Recliner (~ACE_Recli@c-50-165-178-74.hsd1.in.comcast.net) joined #forth 12:56:41 --- quit: karswell (Read error: Connection reset by peer) 12:58:49 --- join: karswell (~user@158.208.208.46.dyn.plus.net) joined #forth 13:08:05 --- quit: LeCamarade (Ping timeout: 256 seconds) 13:08:49 --- join: LeCamarade (~revence@139.59.111.106) joined #forth 13:15:43 --- quit: ACE_Recliner (Ping timeout: 264 seconds) 13:18:14 --- join: ACE_Recliner (~ACE_Recli@c-50-165-178-74.hsd1.in.comcast.net) joined #forth 13:57:34 --- quit: gravicappa (Ping timeout: 268 seconds) 14:27:04 --- quit: Bunny351 (Quit: Bunny351) 14:27:24 --- join: Bunny351 (~Bunny351@p4FF18F76.dip0.t-ipconnect.de) joined #forth 14:29:31 --- quit: GeDaMo (Remote host closed the connection) 14:53:38 --- quit: true-grue (Read error: Connection reset by peer) 15:47:38 --- quit: impomatic (Ping timeout: 246 seconds) 16:56:30 --- quit: nighty (Quit: Disappears in a puff of smoke) 16:59:38 --- quit: dys (Ping timeout: 260 seconds) 17:12:27 --- quit: proteusguy (Ping timeout: 240 seconds) 17:18:07 --- quit: karswell (Ping timeout: 264 seconds) 17:28:35 --- join: Zarutian (~zarutian@168-110-22-46.fiber.hringdu.is) joined #forth 17:31:55 --- join: wa5qjh (~Thunderbi@121.54.90.150) joined #forth 17:41:40 pointfree: from reading an r/Forth comment you made, you seem to be somewhat familiar with Complex Programmable Logic Devices, no? 17:43:01 Zarutian: Yes. 17:44:34 I get that they are rather diffrent than FPGAs, which are basically like JK-flipflop bufferd LUTs and routing-switch boxes. 17:45:34 What I am wondering about is the ease of use differences between FPGAs and CPLDs 17:47:23 I don't know as much about FPGA's but afaik FPGA's are composed of truth-tables/lookup tables, and CPLD's are composed of PLD's each with AND arrays feeding into OR arrays feeding into macrocells. These PLD's are embedded in a routing fabric. 17:47:46 for instance is the bitstream (or what ever it is called) more easily understandable when dealing with CPLDs? I take they are basically GALs/PALs/PLAs 17:48:28 macrocells? What kind of hardwired gates andor functions do these macrocells provide? 17:51:37 The macrocells can provide registered/sequential logic capabilities to the outputs of the OR array. 17:53:13 oh, so stuff like JK-flipflops, counting registers, shifting registers and such. 17:53:40 yes 17:56:21 https://06cf5199-a-62cb3a1a-s-sites.googlegroups.com/site/ustics131/pld/PLD%20006.jpg https://github.com/azonenberg/openfpga/wiki/PLD-Configuration#macrocell-architecture 17:56:31 I take that CPLDs can often be much faster at responding to signal changes than FPGAs? (Because there isnt something like address decoding added to the propagation delay) 17:56:46 --- join: proteusguy (~proteus-g@125.162.138.147) joined #forth 17:56:46 --- mode: ChanServ set +v proteusguy 17:59:21 that .jpg you linked is basically an PAL (or one of these three I mention earlier) basically Sum-of-Products kind of deal if I recall my combinatroy boolean logic correctly 17:59:58 Yes. Faster response and more predictable delays. 18:00:25 excelent for hard hard realtime systems then? 18:02:15 --- quit: dual (Quit: If at first you don't succeed, skydiving is not for you.) 18:04:25 Yes, better than FPGA's for that purpose. 18:06:09 --- quit: Bunny351 (Ping timeout: 256 seconds) 18:06:13 any vendors or brandlines of CPLDs you generally recommend? 18:09:58 Zarutian: I'm using the PSoC 5LP because it also has a UAB array for analog front-ends. The PSoC 5LP devkit is cheap cheap cheap (10USD). I don't have experience with others, but I'm sure others on ##openfpga have a wider experience with CPLD's than me. 18:10:38 what does UAB stand for in this context? 18:10:50 Universal Analog Blocks. 18:11:18 configurable and routable analog. 18:11:37 UDBs = Universal Digital Blocks. 18:13:42 basically muxes that can route analog signals. Only that or are there also ADCs? 18:14:48 There is an analog routing fabric. It supports analog front-ends. So not just ADC then DSP. 18:15:38 I was looking at FPAA's when someone told me I would get more analog by using the PSoC 5LP. 18:16:48 Cypress also has a dedicated analog coprocessor http://www.cypress.com/products/psoc-analog-coprocessor 18:16:52 I meant, does it only do the routing via the muxes or does it also offer ADCs capability 18:17:05 oh, neat 18:17:52 It has ADC's and DSP as well if that's what you're asking. 18:18:27 Also routing does not so much work with muxes as it does with short-circuiting. 18:18:35 (on the PSoC) 18:18:37 Flash ADCs or successive aprox ADCs? 18:19:28 Should check out #dirtysand for a friend's Flea board which is an excellent FPGA starter kit(s). 18:20:14 the former is expensive as hell (each possible value has its own dedicated fast compartor) while the latter is much cheaper but does have lower maximum sampling frequency 18:21:47 talking about ADCs, I noticed a implementation gap that most should have seen. Two hints I am going to give, look at Sigma-Delta ADCs and look at bitplanes. 18:24:50 * Zarutian muses if there are FRAM based instead of Flash based CPLDs aviable. He hopes that Texas Instruments had promisiously licensed that FRAM tech to CPLDs makers. 18:25:34 Reducing ADC Sampling Rate with Compressive Sensing: https://arxiv.org/abs/1503.00311 18:25:34 Regime Change: Sampling Rate vs. Bit-Depth in Compressive Sensing: http://www.ece.rice.edu/~jnl5066/papers/thesis.pdf 18:25:34 New Approach Based on Compressive Sampling for Sample Rate Enhancement in DASs for Low-Cost Sensing Nodes: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4239930/ 18:25:48 http://www-personal.umich.edu/~romanv/slides/2007-UCD-CS.pdf (compressed sensing intro) 18:26:31 There. I spilled the beans about what I plan to do with this. 18:28:03 It's still to be determined if a compressed sensing setup can be done with existing hardware. 18:33:41 --- join: nighty- (~nighty@d246113.ppp.asahi-net.or.jp) joined #forth 18:36:51 --- join: neceve (~ncv@unaffiliated/neceve) joined #forth 18:37:03 Zarutian: afaik fram cplds would be slower than these sram cplds at the moment. 18:37:47 pointfree: well, I am mainly thinking about the configuration being kept in fram cells instead of flash cells. 18:39:04 but yeah SRAM CPLDs are probably more dynamically reconfigurable than FRAM or Flash ones. 18:39:23 Zarutian: for persisting the configuration when the power is off and then configuring the CPLD memory at startup? 18:39:46 yeah 18:40:21 many CPLDs actualy use Flash cells and not SRAM cells to keep the config 18:41:14 Well you could attach an FRAM and have it mapped to 0x60000000 (0x800000 bytes of it) 18:41:47 hence these kind of CPLDs can start working right when the powersupply has become stable as there is no loading nescisarly. 18:43:59 I was thinking of putting a capacitor on the board so that when the power is cut, there will be just enough charge in the capacitor to persist the configuration to flash (or other). 18:47:11 do not know about flash as it is rather energy hungry (well the erasing part at least) but well doable with fram I think 18:48:24 hm. good to know. 18:50:39 Now that you say that I guess it would make sense to use the flash for the core of the system that does not change much and use fram as a user area for source code, settings etc. 18:51:38 silly question... when maintaining a buffer, would it make more sense to keep track of the address of the next-available part of it (HERE style) or the amount of it that's already used? 18:52:25 or, alternatively, the number of "things" that are in it (cells, structs, etc)? 18:53:30 in my experience it's more convenient to have a write pointer, or a next destination address, however you want to call it, and then at the end subtract to turn it into a length. but obviously you might write your code differently than I do and in your case maybe it's more convenient to track an index 18:54:24 reepca: I'm in favor of only keeping around information you need: the next available "thing" 18:54:30 reepca: depends. How much is allotted to that buffer? Do you check that stuff does not overrun it? 18:54:50 The issue is just that turning a byte length into a "number of things" count involves a divide, and an assembly class last semester and the related reading on stackoverflow made me a bit paranoid about how long division takes 18:55:02 the buffer is relatively small compared to the dictionary as a whole, yes I need to check that stuff doesn't overrun it 18:56:19 The idea is to hold vertices in there so that I can use simple shape-drawing calls but still get batching advantages (once it would overrun, it does the actual opengl call and resets the buffer) 18:58:25 it's only one division, though. you're not dividing in a tight loop 18:58:34 the alternative is to multiply in the inner loop 18:59:08 Good point 19:17:08 --- join: vsg1990 (~vsg1990@static-72-88-80-103.bflony.fios.verizon.net) joined #forth 19:29:59 --- join: [X-Scale] (~ARM@214.20.108.93.rev.vodafone.pt) joined #forth 19:31:46 --- quit: X-Scale (Ping timeout: 260 seconds) 19:31:46 --- nick: [X-Scale] -> X-Scale 19:45:26 --- quit: ACE_Recliner (Ping timeout: 258 seconds) 19:47:34 --- join: smokeink (~smoke@123.114.74.87) joined #forth 19:50:06 --- quit: Zarutian (Quit: Zarutian) 20:43:10 --- quit: smokeink (Ping timeout: 260 seconds) 20:48:03 --- join: ravi` (~user@70-36-62-124.dyn.novuscom.net) joined #forth 20:48:16 hi all 20:48:36 does anyone know how to use branch primitives directly in gforth? 20:48:50 I would like to understand how conditionals and loops are implemented 20:50:55 I assume you've already looked at 5.8.6 of the gforth manual "arbitrary control structures"? 21:05:13 I have - maybe I am not understanding it, but I would like to know how if is implemented for e.g. 21:06:55 SEE IF gives me : IF ['] ?branch compile, >mark ; immediate compile-only 21:08:31 --- quit: neceve (Quit: Konversation terminated!) 21:09:19 ?branch being a primitive implemented in machine code (specifically, compiled from C) that does the actual conditional branch, I would assume, and >mark being a word that leaves where to patch in the forward branch address on the control stack 21:10:33 (because it doesn't know where to skip to in the case of FALSE until a THEN is encountered, so it just sets aside some space for THEN to put the destination in once it is encountered0 21:10:41 ) 21:12:32 got it, thanks 21:13:50 --- quit: vsg1990 (Quit: Leaving) 23:13:13 --- join: dys (~dys@ip-109-40-3-231.web.vodafone.de) joined #forth 23:29:23 --- quit: Keshl (Read error: Connection reset by peer) 23:29:45 --- join: Keshl (~Purple@24.115.181.94.res-cmts.gld.ptd.net) joined #forth 23:51:28 --- join: true-grue (~true-grue@176.14.222.10) joined #forth 23:59:59 --- log: ended forth/17.03.15