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Here's a few articles about debuggers (there's more if you search around): http://www.forth.org/fd/FD-V06N3.pdf#page=32 http://www.forth.org/fd/FD-V05N1.pdf#page=19 05:16:39 --- quit: irsol (Ping timeout: 250 seconds) 05:17:53 ofw and cforth have nice introspection words: http://wiki.laptop.org/go/Forth_Lesson_5 and debugging words: http://wiki.laptop.org/go/Forth_Lesson_15 05:20:35 --- join: irsol (~irsol@unaffiliated/contempt) joined #forth 05:27:22 We had nice tools for multicore debugging (with async break points) on SEAforth :) 05:28:25 --- quit: irsol (Ping timeout: 256 seconds) 05:29:43 But I've used them mostly for test beds, to get input/output data and for probes. I think it's more important to become a good programmer, not a good user of the debugger. 05:32:23 --- join: DocPlatypus (~skquinn@c-73-6-60-72.hsd1.tx.comcast.net) joined #forth 05:32:35 --- join: irsol (~irsol@unaffiliated/contempt) joined #forth 05:32:38 yeah, I've never used a forth debugger myself. 05:40:53 --- quit: irsol (Ping timeout: 256 seconds) 05:43:39 --- join: irsol (~irsol@unaffiliated/contempt) joined #forth 05:45:57 --- join: nighty (~nighty@s229123.ppp.asahi-net.or.jp) joined #forth 05:54:52 --- quit: irsol (Ping timeout: 268 seconds) 05:58:07 --- join: irsol (~irsol@unaffiliated/contempt) joined #forth 06:06:03 --- quit: irsol (Ping timeout: 250 seconds) 06:09:15 --- join: irsol (~irsol@unaffiliated/contempt) joined #forth 06:10:17 --- join: workp (~workp@host-84-13-110-11.opaltelecom.net) joined #forth 06:19:52 --- quit: irsol (Read error: Connection reset by peer) 06:20:40 --- join: irsol (~irsol@unaffiliated/contempt) joined #forth 06:24:09 --- join: karswell` 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12:37:46 --- join: mat4 (~Claude@ip5b4101eb.dynamic.kabel-deutschland.de) joined #forth 12:39:36 hello 12:39:47 mat4: hi 12:39:55 hi gordonjcp 12:41:17 I want to hint to this talk: https://www-users.cs.york.ac.uk/chrisb/main-pages/stack-machines/stack-machines-research-page.html 12:41:31 it's worth reading in my opinion 12:42:47 sadly the presentation does not seemed to be recorded 12:44:58 --- join: irsol (~irsol@unaffiliated/contempt) joined #forth 12:45:47 mat4: what is it about beyond just what can be infered from the url? 12:50:24 --- quit: irsol (Ping timeout: 258 seconds) 12:53:50 The authors demonstrate that the current research opinion against stack architectures is and was simply wrong, though experimental out-of-order superscalar stack architectures 12:54:51 which shows comparable characteristics to recent register based designs 12:55:02 what was that opinon again? the current research one 12:56:16 that stack architectures are inferior to register based designs because of the sequential nature of stack based machine code 12:56:32 aah, that 12:56:58 --- join: irsol (~irsol@unaffiliated/contempt) joined #forth 12:57:27 the main issue I have against register based designs is that the registerfile needs to be multi ported (if the file is bigger than 16) 12:58:49 there investigated in some historical research conclusion that relevant authors for this belief simply copied the opinion of Patterson which was not experimental verified 12:59:16 sorry, let me formulate again: 12:59:23 and also that the range of operations in register based design entails so much decoding delay that it needs out of order execution to try to regained what was wasted. 12:59:57 there investigated a historical research with the conclusion that relevant authors for this belief simply copied a side noted opinion of Patterson which was not experimental verified 13:01:10 I have no idea who this Patterson is or was 13:01:35 So, what is the name of the fastest stack processor in the world? Let's compare its performance with ARM :) 13:01:55 true-grue: hmm.. RTX2010? 13:02:20 --- quit: irsol (Ping timeout: 260 seconds) 13:02:36 true-grue: it is pretty fast at responding to external events. Though it might not be the most throughputfull. 13:02:55 Zarutian, a designer of the first RISC processors 13:03:44 well he got one thing right, getting rid of many of the various 'addressing modes'. 13:04:07 I think so 13:05:16 on the other side, this also lead to increased code size (which is regardless a natureal weak point of most RISC architectures) 13:06:23 efficient cache usage is a very complicated topic 13:06:35 ^complex 13:07:00 mat4: he probably never heard of a long standing design principle that has been in electronics for decades now. Only recently it got a good describing name: hierchial modularity. 13:07:55 how big are these caches now days? 128 KiBiBytes? 13:07:58 Zarutian, Is it faster than PSC1000? 13:08:19 aka ShBoom aka Ignite. 13:08:39 true-grue: the RTX2010? I am not that familiar with PSC so I cant tell. 13:08:53 I see. 13:09:25 Zarutian, first level caches seem independent of there size always to small ;) 13:09:59 --- join: irsol (~irsol@unaffiliated/contempt) joined #forth 13:10:31 the software complexity and program sizes demands will regulary grom faster 13:10:38 ^grow 13:11:22 true-grue, I think that's a VLIW architecture used for (militsry) space applications 13:11:23 mat4: I just get the hunch that all the complex caching takes up more die space than just the equiv sized SRAM. I rather page in and out whole pages than just 64 bytes at a time. 13:11:46 not to forget the increase in power usage 13:12:16 the whole concept is known to be not very efficient 13:12:38 fuck efficiency 13:12:45 you want reliability 13:12:48 just think about it, caching is basically trying to emulate faster bigger memory 13:13:05 however, for superscalar out-of-order architectures caches are a main performance factor 13:13:08 I wonder if you could think of cache as a kind of special case of writable control store 13:13:39 gordonjcp: you are thinking of instruction cache in this case? 13:13:49 mat4, It's not VLIW. You may read about it here: http://www.dei.isep.ipp.pt/~nsilva/ensino/ArqC/arqc2004-2005/AulasPraticas/Processador%20Ignite%20(Reference%20Manual).pdf 13:14:03 no not that one 13:15:04 --- quit: irsol (Ping timeout: 246 seconds) 13:15:48 * Zarutian wonders how many RTX2010 cores&memories you could fit on a square centimeter using current fab processes. 13:17:03 rtx2010 -> m17 -> f21 -> seaforth40 -> ga144 13:18:04 well, I do not like F18 arch that much. I rather have something that can run an entire Forth system on each core&memory 13:18:28 ga has 144 cores on 21 mm^2. 13:18:43 It's 180 nm. 13:19:03 yeah but only 64 sram & 64 rom cells per core 13:20:48 Well, it's more than the most of reconfigurable arrays have. 13:21:07 true that 13:21:08 Take FPGA, for example :) 13:21:50 in addition you will have some difficulties to compare a 'analog' design like the GA144 performance wise with typical ARM MCU'S 13:22:53 --- join: irsol (~irsol@unaffiliated/contempt) joined #forth 13:23:35 well, one observation I heard was GA144 and FlowBasedProgramming would be pretty good fit. 13:24:32 mat4: typical ARM MCU's eat through battery or supercap charge pretty greedly and quickly 13:25:46 yes, the GA144 is very power efficient 13:25:53 mat4: wouldnt be surprised if an GA144 could perform for weeks on one 9v alkaline battery while ARM MCUs only have days. 13:26:51 probably, never tried that 13:27:21 like one of the Mill guys like to say, you can get lot of performance out of modern x86 if you have enough freon to cool it. 13:28:28 --- quit: irsol (Ping timeout: 252 seconds) 13:30:52 there should work better finsihing long awaited prototype implementations than publishing such statements 13:31:04 ^finishing 13:31:59 sure, but he was known for saying that before there was even a glint of the design family now called Mill 13:34:05 it can be that these statement is a reaction of a public presentation, where a nitrogen cooled Pentium 4 was showed at I think somewhere about 7 or 8 GHz clock frequency 13:34:06 --- join: irsol (~irsol@unaffiliated/contempt) joined #forth 13:34:14 what has irritated me and still does is the phase-space blindness of many designers|engineers|programmers|etc and unwillingness to ask 'why is this so? what are the assumptions made when the design methodology came about' and such. 13:35:43 that are simply limitations of more recent design tools (or better component design environments) 13:36:17 many times when I ask such people I get the answer "well, we have always done it this way. Or my professor always did it this way" 13:37:32 a general disadvantage of human inertia in my opinion 13:38:14 Independent thinking requires energy 13:38:27 so scholastic research is prefered 13:40:17 ;) 13:40:37 --- quit: irsol (Ping timeout: 264 seconds) 13:40:58 take for instance the ourogensis of huge basic blocks of instructions. Somebody noticed that much of, at the time, code was mostly straight line with few branches. To speed up such code many design decisions were taken in certain way. 13:41:25 Now days the only way to get performat code is to try to shoehorn it into the mold of said straight line code with few branches. 13:41:47 performant* 13:43:09 which means heavy use of inlining which means higher instruction cache pressure which means bigger die area dedicated and more power consumed. 13:43:24 I agree 13:44:24 a good reason prefering stack based designs which allow effective subroutine factored compilation 13:45:44 heck, I saw a few years back an implementation of a small vm that had made many 'cores' through the use of many SIMD instructions where the only branching was a unconditional jump back to the begining of the loop where those SIMD instructions were inside of. 13:46:19 --- quit: koz_ (Quit: WeeChat 1.6) 13:47:41 --- join: koz_ (~koz@121.99.240.58) joined #forth 13:48:44 mat4: not only more effective subroutine factored compilation but also finding out heavily used subroutines and implementing them as instructions if it was warranted. 13:51:03 Zarutian, that was probably a design from me (I've experimented with these approach some time ago). I have the WISC16 documentation still here 13:51:08 heck, if there is an reconfigurable array avialable in the core then said specialized instruction|subroutine implementations can be swapped in and out. 13:51:35 --- join: irsol (~irsol@unaffiliated/contempt) joined #forth 13:51:57 mat4: probably from you but I have also seen it used to implement an 6502 variant. 13:53:06 hmm, no. If this where my design I would have implemented a 6809 variant :) 13:54:25 the point is that this is rather obvious to people that do not mind looking at such problems from more than just a few perspectives. 13:54:41 however, instruction compilation to reconfigurable logic is a main topic of a future talk from me in January 13:55:13 mat4: is that talk going to be recorded? 13:55:17 yes 13:55:47 I present my current CPU design 13:57:21 mat4: I am curious how you deal with the priviledged|kernel and problem|user mode seperation, if you use that at all that is. 13:58:16 --- quit: irsol (Ping timeout: 258 seconds) 13:58:25 Do you know the Singularity project from Microsoft ? 13:58:30 This way 13:59:00 yes, I know of it and that it used seperation through trusted compiler. 13:59:20 or more likely trusted linker&assembler. 13:59:52 I see no use in supporting obsolete operating-system architectures which depend on special ISA support 14:00:28 where a modern compiler environment is more than sufficient 14:01:33 anyhow, the ISA is extensible at runtime 14:03:10 so there are no limitations in configurating special instruction sets for such purposes 14:03:44 --- join: irsol (~irsol@unaffiliated/contempt) joined #forth 14:04:39 heck, I have seen an dual stack machine CPU design where the only protection supported hardware wise (the bare minimum) was trap-on-instruction and pretty fast mode switching from trapping and untrapping. User code ran slightly slower but not by much. 14:06:19 that's not uncommon for early CPU architectures 14:06:31 this had vectored interupts/traps where if you left all zeros in the vector that interrupt/trap was ignored and execution just continued onto next instruction instead of taking the trap/interrupt. 14:08:26 interesting concept. Thaks for sharing! 14:08:31 ^Thanks 14:09:00 --- quit: irsol (Ping timeout: 248 seconds) 14:11:10 this was in a paper, which regretfully I do not remember who authored or the title, where the author(s) were looking into what the smallest support for protection could be. 14:12:35 a 'kernel' of a Forth system could defend itself and support memory segmentation (though not relocation) and preemptive task switching. 14:13:32 I see the main advantage of these concept in it minimal implementation effort 14:13:56 they noted that if you had this processor connected to memory where part of the address space is bank switched you could easily keep tasks seperated. 14:14:21 minimal hardware implementation effort and maximal flexibility of protection implementation. 14:14:35 hmm, there had probably a barrel architecture in mind 14:14:44 yes 14:15:42 then take a look here: https://opencores.org/project,hive 14:16:10 --- join: irsol (~irsol@unaffiliated/contempt) joined #forth 14:20:40 the architecture I described was 16 bit through out. They also thought of using an simple ContentAddressableMemory for simple MMU (256 entries of 256 cell pages.) 14:22:10 (basically the upper address byte was substituded) 14:23:00 --- quit: irsol (Ping timeout: 268 seconds) 14:33:23 --- join: irsol (~irsol@unaffiliated/contempt) joined #forth 14:34:54 ok, segment addressing 14:39:39 --- quit: irsol (Ping timeout: 258 seconds) 14:45:17 I just read that the total die area for internal SRAM of one Epiphany-IV core is 53,3 % 14:45:44 followed by the register file which requires additional 12,9 % 14:46:29 ... outch! 14:48:25 I think the fabric process must be < 30 nm 14:49:12 --- join: irsol (~irsol@unaffiliated/contempt) joined #forth 14:49:19 ciao 14:49:22 --- quit: mat4 (Quit: Verlassend) 14:55:46 --- quit: irsol (Ping timeout: 258 seconds) 15:02:14 --- join: irsol (~irsol@unaffiliated/contempt) joined #forth 15:08:13 --- quit: irsol (Ping timeout: 264 seconds) 15:13:48 --- quit: true-grue (Read error: Connection reset by peer) 15:17:38 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