00:00:00 --- log: started forth/15.03.04 00:26:35 --- join: fox__ (~fox@118.244.190.36) joined #forth 01:52:22 --- quit: gabriel_laddel (Ping timeout: 250 seconds) 02:02:52 --- join: gabriel_laddel (~user@unaffiliated/gabriel-laddel/x-9909917) joined #forth 02:06:36 --- quit: fox__ (Quit: fox__) 02:20:02 --- join: nighty^_ (~nighty@hokuriku.rural-networks.com) joined #forth 02:21:04 --- quit: nighty^_ (Client Quit) 02:23:48 --- join: nighty-_ (~nighty@hokuriku.rural-networks.com) joined #forth 02:27:11 --- join: proteusguy (~proteusgu@180.183.98.197) joined #forth 02:27:11 --- mode: ChanServ set +v proteusguy 02:55:14 --- quit: bluekelp (Remote host closed the connection) 02:57:12 --- quit: impomatic (Quit: http://retroprogramming.com) 03:10:35 --- join: true-grue (~grue@95-27-139-21.broadband.corbina.ru) joined #forth 03:54:01 --- join: Zarutian (~Adium@168-110-22-46.fiber.hringdu.is) joined #forth 04:06:14 --- quit: gabriel_laddel (Remote host closed the connection) 04:37:32 howdy all - my kubuntu setup went all squirrelly on me so it's taken 2 days to rebuild from scratch. I miss anything interesting? 04:44:29 not much... mozilla announced they were dropping support for javascript in favor of colorforth... 04:47:07 Yeah, but it was just punctuation Forth with colour coding for the punctuation. More like syntax highlighting than real colorForth. 04:50:15 ttmrichter: you up for discussion on designs of computer architectures? 04:50:31 Some, sure. 04:50:56 I'm not really a hardware kind of guy, but as a USER of these things I have a few (somewhat educated) opinions. 04:52:22 one thing that seems strange to me is the whole pipelineing, branch prediction and such as that seem to arise from a single assumption: that address space is flat and has same access delay. 04:53:35 16 KiloByte (KB=1024) of fast SRAM isnt that expensive, nor is a simple DMA circuitry to swap to slower bigger DRAM 04:54:35 you think that such a machine would be too hard to program for? 04:54:45 Isn't that how a cache works? 04:55:27 I mean my CPU now has two L1 caches at 32K. I'm pretty sure it's SRAM. 04:55:28 cache not only has SRAM in the memory word section but also in the address decoding section. 04:55:45 And the L2 at 256KB and the L3 at 3MB. 04:56:17 what these caches try to do is hiding the high latency of the main memory 04:56:47 Right. 04:57:10 which means that they are designed with certain unstated assumptions on distribution of memory accesses 04:57:25 Well the CPU is *designed* that way. :) 04:57:38 So it's not an assumption. It's flat-out stated in the design. 04:57:41 (fetching an instruction is also an memory access btw) 04:57:50 right 04:58:24 what I am really mulling over is: is that set of assumption limiting the computing platform in ways unknown to us? 04:58:31 Very likely, yes. 04:58:37 It's a leaky abstraction. 04:58:58 it is a very leaky abstraction in my opinion. 04:59:12 Try, for example, to do anything with hard real-time constraints on a system with umpteen levels of cache of varying speed and size. 04:59:28 A friend of mine did that for a living at what used to be Alcatel. 04:59:35 (Alcatel got sold, right?) 04:59:43 He was a BRILLIANT mathematician. 04:59:55 simple, I put an PIC/AVR/MCU that does the hard real time stuff. 04:59:59 Like the kind that gathered a bunch of scholarships through his entire academic career. 05:00:15 And it was his grade of smarts needed to analyze Alcatel's switch performance. 05:00:37 It's the usual problematic cycle: 05:00:40 switch? as in Ethernet switch or switching fabric inside a chip? 05:00:48 ATM switch. 05:00:54 Massive mainframe monstrosities for telcos. 05:01:09 1. You make a simple architecture. 05:01:14 Asynchronus T-something M-something 05:01:22 Asynch Transfer Mode. 05:01:35 anyway go on 05:01:38 2. People learn (and internally normalize) that architecture. 05:02:03 3. The limits of the architecture are hit. 05:02:27 4. People use work-arounds (like hard segmentation, overlays, etc.). 05:02:50 5. People complain that those work-arounds are "too complex". (Because it doesn't match the simple model they've internalized.) 05:03:04 6. Designers write "simplification" and "abstraction" layers over this. 05:03:13 I know what overlays are (basically bank-switching for DLLs/.SOs) but what is hard segmentation? 05:03:40 7. Problems are buried under murky, often undocumented abstractions that are poorly understood by the users and thus ... they write waaaaaay suboptimal code. 05:03:53 Think the old MP/M machines. 05:04:02 not familiar with those 05:04:11 16KB of space for the MP/M control program and multiple 48KB banks for users. 05:04:12 MasterProgram/M something? 05:04:21 Multi-user CP/M. 05:04:58 I see and each user got a x KB bank for themselfs? 05:05:10 The issue being that neither the user software nor the system software was shielded from the fact that they were operating in an environment that could switch out from underneath them without notice. 05:05:15 Basically. 05:06:17 surely the task switching code kept user stacks/registers and such in well know memory location in each user bank? 05:06:31 Pretty much. 05:07:39 so the only issue is then the load (how many tasks/users are on) and slice length? 05:07:51 But the nature of it was such that things CP/M programmers were always doing had to be cut off. 05:08:15 examples of such things? 05:08:29 Loads of crap in modifying the kernel's parameters. 05:08:37 CP/M was a single-user system. 05:08:39 This was legal. 05:08:47 I see, 05:08:54 Things like overwriting system call handlers with your own handlers. 05:09:51 surely the kenernel bank could be made write protected and such. 05:10:27 Could be. Wasn't in the machine I owned. :) 05:10:32 but that is complexifing the simple architecture CP/M started out with 05:10:38 Right. 05:10:58 CP/M was a single-user operating system and MP/M was pretty much a hack. 05:11:05 One that tried to pretend to be CP/M but wasn't. 05:11:16 And this "simplification" to make it "easy to port" was a problem. 05:11:43 This is why CPUs started developing MMUs, MPUs, etc. 05:11:45 they should have gone the IBM 360 way and just have VMs. One per user, each running a CP/M ;-) 05:11:56 On a Z80. Riiiiiiiiiiiiiiiiiiiiiight. :D 05:12:08 MPUs? 05:12:19 Memory Perhipiral Unit? 05:12:20 Memory Protection Unit. 05:12:25 I see 05:12:41 MMUs and MPUs used to actually be external devices. 05:13:13 yeah, saw an ad in old Forth magazine on how to splice such a device in between the CPU and main memory 05:15:30 and stuff in CPUs from that time like a input pin on cpu for such a device to issue an cpu fault. 05:15:40 Yep. 05:16:10 In some ways the older CPUs were more flexible than modern ones in terms of supporting new hardware innovations. 05:16:27 --- quit: Bahman (Quit: Ave atque vale) 05:18:16 right, for instance you could have a few CPUs each with a 16KB memory on seperate buses that interrupted another CPU that did hardware multiplexing for them. 05:20:15 or have one CPU with an MPU that supported big banks of memory and memory mapped a 'bank switch' address register. (Basically extending the address space with an address space identifier) 05:22:27 heck most of computer security ?boils down/reduces/recursive-base-cases? of what the MPU is doing. 05:24:05 the only way to run untrusted code on something like a Z80 machine that is without a MPU or MMU is to compile it at load time on the machine that is to run it. 05:43:53 OK, I found it. 05:44:19 "However the address and data buses were multiplexed and the chip was, also in other respects, somewhat complicated to program and interface to. Calculation of exact execution times was also very much harder to do than for the Z80." 05:44:35 "Hitachi developed the HD64180, which is a less ambitious Z80 derivative that has had great success, probably because it is almost as simple to program and interface to as the original Z80." 05:44:58 This is why they keep slathering abstractions and simplifications over hard things. 05:45:21 The Z800 failed. The HD64180 succeeded. Almost, but not quite, only because the Z800 was harder to program. 05:45:56 I wonder how they multiplexed the address and data buses on same pins. 05:46:15 Probably a lack of pins. 05:46:36 Packaging limitations or just too expensive to make the silicon for the time. 05:48:58 I think packaging limitations but hell, having an 16 bit wide bus for both addresses and data and three strobe pins wouldnt be that hard to interface to. Specialy if you use two latch chips to demultiplex them into address and data buses. 05:49:39 (one strobe pin for address, one for read access and one for write access.) 06:01:33 --- quit: karswell` (Remote host closed the connection) 06:07:51 --- join: xyh (~xieyuheng@2001:250:3002:5550:6ea1:cc0f:bcb2:b187) joined #forth 06:21:34 --- quit: nighty-_ (Quit: Disappears in a puff of smoke) 06:22:08 --- join: nighty-_ (~nighty@hokuriku.rural-networks.com) joined #forth 06:27:52 Zarutian: That level of detail is beyond my meagre skills set. 06:28:11 I'm a humble programmer. For most of my career I drew a hard line at "if I have to know voltage levels, I'm one level of abstraction too low". 06:28:22 Lately that boundary has softened. A lot. 06:28:38 But still, design decisions on that order go way over my head. 06:30:51 ttmrichter: there is a site http://allaboutcircuits.com/ that might intrest you 06:39:24 Yeah, I know a couple of such sites plus a really comprehensive online textbook. 06:39:29 The issue is time and space. 06:40:17 aah, I see 06:40:20 (All About Circuits is actually in my bookmarks, to be clear.) 06:42:51 I remember reading about switch bounce and screaming when I read the solutions to it that DIDN'T involve me manually counting times across transitions. 06:45:38 --- join: mnemnion (~mnemnion@c-98-210-219-91.hsd1.ca.comcast.net) joined #forth 06:47:12 oh, that. Basically wait a bit and sample it input again. 06:47:37 that or use a schmitt trigger 06:48:59 No, I needed a software solution because the hardware was not modifiable. 06:49:22 So I had to sit there and detect the transition, then count out enough time for it to be considered "real". 06:49:45 Which meant sitting there with a 'scope (I HATE THINGS THAT REQUIRE SCOPES!) to see how long the noisy period was. 06:50:16 So when I found out that a simple filter can settle the problem nicely I screamed at the jerk who designed the board without such a filter. 06:56:42 let me guess, the guy was trying to keep the number of components down due to bean counting reasons 07:01:45 ttmrichter, haha (re:javascript->colorforth) actually I've been looking at asm.js a bit as a possible target for a forth-ish language. I abhor javascript so it would be interesting to be able to do concatonative programming inside the browser at near compiled C speeds. 07:02:31 * Zarutian thinks of compiled C/C++ speeds as medium slow. 07:03:16 Zarutian: It was a cheap demo board. 07:03:52 This one: http://i.imgur.com/D9FKXnt.jpg 07:04:14 No, wait. Wrong one. 07:04:40 Don't think I have a picture of mine. I'll show you the purchased source. 07:05:10 http://item.taobao.com/item.htm?id=18823653550 07:05:26 There's two buttons on that thing. One's a reset button. The other's a user button. 07:05:33 The user button is unbuffered in any way. 07:05:45 *AND* it's a super-tough one. 07:05:50 So it bounces like crazy. 07:15:31 yeah they tend to do that. And never in the completely same way. 07:17:27 Zarutian, so what are your typical definitions of fast speeds and what tech do you build it upon? 07:19:25 phonon tech and subnanosec between clock ticks or so. 07:19:51 in all seriousness, FPGAs (which are medium speed to me) or CPLDs 07:20:14 --- quit: djinni (Ping timeout: 250 seconds) 07:20:57 not familiar with CPLDs... how does it differ from FPGA/ASIC? 07:21:10 Complex Programable Logic Devices 07:21:34 I think they are somewhere between FPGAs and ASICs 07:22:46 Coded via verilog/vhdl or something completely different? 07:23:38 verilog/vhdl at the medium level. PLA/PAL matrixes and routing box configs at the lower. 07:28:02 These days there's really no difference between CPLDs and FPGAs. 07:28:13 --- join: djinni (~djinni@105.ip-167-114-152.net) joined #forth 07:28:41 There used to be differences in how they were implemented, but nowadays it seems that CPLDs are smaller FPGAs with slightly less flexible internal layouts. 07:28:45 ttmrichter: FPGAs have synchronus clocked logic. CPLDs dont. 07:29:25 Zarutian: I thought even that difference was slowly disappearing one model at a time? 07:29:34 and most CPLDs are active the moment they get power, no configuration needed to be loaded 07:30:05 (as the config bits are Flash or other non-volatile based iirc) 07:30:22 Zarutian: There are Flash-based FPGAs these days too, though. 07:30:41 The lines are so blurry it's hard to find anything that solidly distinguishes between them. 07:30:58 Except that FPGAs of a given generation tend to be larger than CPLDs of the same generation. 07:31:06 (But new CPLDs can often be larger than old FPGAs.) 07:32:04 --- quit: joneshf-laptop (Ping timeout: 252 seconds) 07:32:12 well, FPGAs are made up of slicesections while CPLDs are made up of SimpleProgramingDevices (GAL/PAL/PLA/whathaveyou) 07:32:32 Right. That's the "less flexible internal layout" thing I was talking about. 07:34:55 what I havent seen is (N)OR cell matrixes whose config is clocked in serially through. (The config bits per cell is connected together in hilbert curve) 07:42:11 --- quit: darkf (Quit: Leaving) 07:46:17 --- join: ASau` (~user@46.114.151.33) joined #forth 07:50:02 --- quit: ASau (Ping timeout: 252 seconds) 08:14:16 --- join: blandflakes (4815c640@gateway/web/freenode/ip.72.21.198.64) joined #forth 08:16:07 --- quit: blandflakes (Disconnected by services) 08:16:40 --- join: blandflakes (4815c642@gateway/web/freenode/ip.72.21.198.66) joined #forth 08:48:16 --- join: johnmark_ (~johnmark@c-73-51-235-57.hsd1.il.comcast.net) joined #forth 08:50:16 --- quit: mnemnion (Remote host closed the connection) 09:24:18 --- quit: xyh (Remote host closed the connection) 09:24:18 --- quit: proteusguy (Ping timeout: 246 seconds) 09:35:30 --- join: impomatic (~chatzilla@61.205.125.91.dyn.plus.net) joined #forth 09:37:05 --- join: proteusguy (~proteusgu@ppp-110-168-229-39.revip5.asianet.co.th) joined #forth 09:37:05 --- mode: ChanServ set +v proteusguy 10:10:44 --- join: mnemnion (~mnemnion@c-98-210-219-91.hsd1.ca.comcast.net) joined #forth 10:21:42 --- quit: Zarutian (Ping timeout: 246 seconds) 10:22:51 --- join: kumul (~mool@adsl-72-50-87-22.prtc.net) joined #forth 10:34:12 --- join: fantazo (~fantazo@089144218006.atnat0027.highway.a1.net) joined #forth 11:06:20 --- join: bluekelp (~bluekelp@bluekelp.com) joined #forth 11:06:34 --- mode: ChanServ set +v bluekelp 11:23:18 --- join: ionthas_ (~ionthas@95.85.1.209) joined #forth 11:31:18 --- quit: fantazo (Ping timeout: 246 seconds) 11:32:12 --- join: fantazo (~fantazo@089144218006.atnat0027.highway.a1.net) joined #forth 11:54:35 --- quit: kumul (Quit: Leaving) 12:25:00 --- join: joneshf-laptop (~joneshf@campus-007-250.ucdavis.edu) joined #forth 12:33:10 --- join: Quiznos (~x@c-73-28-150-83.hsd1.fl.comcast.net) joined #forth 12:33:17 rehi 12:34:03 dpans suckith 12:34:08 * Quiznos dux 12:34:12 :> 12:34:39 DIG FTW! 12:34:42 oops 12:34:44 FIG 12:37:50 the forth implementation or the interest group? 12:38:23 grp 12:39:45 sorry about my inculture but what's dig? 12:39:46 in asm, x86, linux port - a pseudo fig forth. 12:39:51 indirect threading. 12:40:01 dig is a typo 12:40:10 thx 12:40:20 shur 13:03:26 --- quit: fantazo (Quit: Verlassend) 13:14:17 --- quit: blandflakes (Quit: Page closed) 13:18:58 --- nick: ASau` -> ASau 13:19:00 --- part: quuxman left #forth 14:01:44 --- quit: bjorkintosh (Remote host closed the connection) 14:04:18 --- quit: nighty-_ (Quit: Disappears in a puff of smoke) 14:05:28 --- join: bjorkintosh (~bjork@ip68-13-229-200.ok.ok.cox.net) joined #forth 14:33:40 --- quit: true-grue (Read error: Connection reset by peer) 14:35:37 --- join: nighty-_ (~nighty@hokuriku.rural-networks.com) joined #forth 14:40:14 --- join: blandflakes (32a9ed08@gateway/web/cgi-irc/kiwiirc.com/ip.50.169.237.8) joined #forth 15:32:50 --- nick: blandflakes -> blandflakes_cook 15:33:02 --- nick: blandflakes_cook -> blandflakes_away 15:39:55 --- join: gabriel_laddel (~user@unaffiliated/gabriel-laddel/x-9909917) joined #forth 15:43:38 --- quit: gabriel_laddel (Remote host closed the connection) 15:44:28 --- join: gabriel_laddel (~user@unaffiliated/gabriel-laddel/x-9909917) joined #forth 15:45:56 --- quit: blandflakes_away (Quit: http://www.kiwiirc.com/ - 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