00:00:00 --- log: started forth/13.12.02 00:50:40 --- join: true-grue (~quassel@37-144-5-22.broadband.corbina.ru) joined #forth 01:18:17 --- join: aranhoide (~smuxi@191.Red-79-157-1.dynamicIP.rima-tde.net) joined #forth 02:30:00 --- quit: ASau (Ping timeout: 246 seconds) 02:37:09 --- quit: kludge` (Ping timeout: 245 seconds) 02:42:39 --- join: kludge` (~comet@unaffiliated/espiral) joined #forth 02:47:09 --- quit: aranhoide (Ping timeout: 245 seconds) 02:50:22 --- join: ASau (~user@p54AFFA8B.dip0.t-ipconnect.de) joined #forth 02:56:59 --- join: aranhoide (~smuxi@0.Red-83-59-7.dynamicIP.rima-tde.net) joined #forth 03:28:44 "Thus within short time you can get a grasp of very powerful parsing techniques." 03:29:00 This presupposes that one *wants* to make one's self ever more distant from the actual target of one's work. 03:29:40 That one *wants* to create artificial structures that make the likelihood of actually *understanding* how the hardware works, what makes it work well, etc. all the harder. 03:29:44 Why? 03:29:55 Because earlier in life one learned some things that make that feel a little easier? 03:30:03 And one hates to change? 03:30:36 Languages like Forth promote a *holistic understanding* of the entire hardware / software system - this tears down the limitations of specialization and encourages greater creativity. 03:31:48 Using Verilog / VHDL to specify hardware designs using software constructs, rather than schematics that give a direct view of what you're actually *doing* is another example of the same sad techniques. 03:32:19 It's all just an example of how badly, badly wrong our overall thought process about *design* has gone. 03:33:29 With languages like Forth the programmer is *directly connected* to how his or her code "embraces" the hardware. 03:33:35 This is an advantage. 03:37:14 With languages like Forth the programmer understands that the hardware and the software are a whole and work together to achieve the desired results. 03:37:17 This is an advantage. 03:39:44 As a manager of engineers developing product lines that had strong embedded technology facets one of the biggest challenges I faced was getting the highly trained software engineers typically available to "get" how to write good software that ran on bare metal. They were too used to having layer after layer after layer of libraries and operating system functions in between them and the hardware. 03:39:57 They just had difficulty "fathoming" what was involved and how to do it well. 03:40:30 Languages like Forth prevent such situations from ever arising by promoting a direct understanding of functionality at all levels of a system. 03:41:30 * aranhoide loving the rant and sad that he missed the beginning 03:42:47 Oh. Morning coffee time and I decided I had some time to waste responding to one of ASau's barbs. "Waste," because it won't affect how he thinks and will merely egg him on. 03:44:17 --- join: LinearInterpol (~RJones@cpe-76-179-150-229.maine.res.rr.com) joined #forth 03:51:31 being close to the metal is only one part of it though, or assembly would be better 03:51:46 By the way, I should caveat my criticism of VHDL / Verilog above - I don't really mean to criticize the textual expression of a hardware design. I'm criticizing the general idea of stating the *behavior* one wants and calling that a hardware design. 03:52:08 Using VHDL or Verilog in a structural way, that maintains a "view" of the hardware modules and how they're interconnected, is just fine. 03:52:16 I don't insist on a "picture" (schematic). 03:59:07 I just find the schematic expression of circuit structures particularly easy for me to work with / optimize / etc., though I will say that the LUT-based nature of modern FPGAs has encouraged me to think in other ways about design optimization. 03:59:48 But that's just because in FPGAs you have no control lower than the LUT level - in a full-custom integrated circuit that "LUT based thinking" would be an impediment to getting the best results. 04:00:30 I'd think that when designing a custom IC one would want to be more directly aware of what one's design decisions were "doing with the transistors." 04:03:46 --- quit: kludge` (Disconnected by services) 04:04:02 --- join: kludge` (~comet@unaffiliated/espiral) joined #forth 04:05:49 --- quit: crc (Read error: Connection reset by peer) 04:06:07 --- join: crc (sid2647@gateway/web/irccloud.com/x-kbaulikdsyizvykx) joined #forth 04:20:31 --- quit: LinearInterpol (Ping timeout: 260 seconds) 04:39:20 --- quit: nisstyre (Read error: Operation timed out) 04:58:42 --- join: nighty-_ (~nighty@lns-bzn-49f-62-147-170-46.adsl.proxad.net) joined #forth 04:59:05 --- join: LinearInterpol (~RJones@WatchGuard.ellsworth-hs.ellsworth.k12.me.us) joined #forth 05:07:41 --- quit: aranhoide (Ping timeout: 264 seconds) 06:32:03 --- mode: ChanServ set +v crc 06:44:13 --- join: vectorman (~vesko@ip-81-193.interbild.net) joined #forth 06:59:57 --- quit: vectorman (Quit: Leaving) 07:23:58 --- quit: I440r (Read error: Connection reset by peer) 07:37:37 --- quit: LinearInterpol (Ping timeout: 246 seconds) 07:50:13 --- join: asie (~textual@178235038113.elblag.vectranet.pl) joined #forth 07:50:25 --- quit: Bahman (Quit: Leaving.) 07:52:14 --- join: Zarutian (~zarutian@194-144-84-110.du.xdsl.is) joined #forth 09:01:55 --- join: Ethical (~sam@139.216.253.31) joined #forth 09:03:11 --- quit: Eth|cal (Ping timeout: 260 seconds) 09:04:08 --- nick: Ethical -> Eth|cal 09:37:09 --- join: LinearInterpol (~RJones@WatchGuard.ellsworth-hs.ellsworth.k12.me.us) joined #forth 09:55:16 --- quit: asie (Quit: I'll probably come back in either 20 minutes or 8 hours.) 10:10:52 --- join: w0rm_x (~w0rm@client-86-25-37-233.midd-bam-1.adsl.virginm.net) joined #forth 10:11:07 --- part: w0rm_x left #forth 10:13:37 --- join: daowee (~daowee@m37-197-73-245.cust.tele2.se) joined #forth 10:36:23 --- quit: Zarutian (Ping timeout: 246 seconds) 10:42:35 --- join: asie (~textual@178235038113.elblag.vectranet.pl) joined #forth 10:47:58 --- quit: LinearInterpol (Ping timeout: 272 seconds) 11:13:19 --- quit: impomatic (Ping timeout: 260 seconds) 12:00:01 --- quit: true-grue (Read error: Connection reset by peer) 12:41:44 --- join: kumul (~mool@67.224.178.69) joined #forth 12:45:16 --- join: nisstyre (~yours@oftn/member/Nisstyre) joined #forth 12:49:30 --- quit: nighty-_ (Quit: Disappears in a puff of smoke) 12:53:12 --- join: impomatic (~digital_w@87.114.102.71) joined #forth 13:08:03 --- join: LinearInterpol (~RJones@cpe-76-179-150-229.maine.res.rr.com) joined #forth 13:09:55 --- quit: asie (Quit: I'll probably come back in either 20 minutes or 8 hours.) 13:17:28 --- join: Chillectual (~RJones@cpe-76-179-150-229.maine.res.rr.com) joined #forth 13:23:08 --- join: aranhoide (~smuxi@0.Red-83-59-7.dynamicIP.rima-tde.net) joined #forth 13:26:37 --- quit: LinearInterpol (*.net *.split) 13:28:31 --- nick: Chillectual -> LinearInterpol 13:35:23 Yes, sure, except one does need it, 13:35:40 unless he's going to waste time on tracking what value is where in the stack or in memory now. 13:36:33 Forth doesn't promote understanding how the system works. 13:37:22 It creates artificial limitations by implementing stack-based VM. 13:37:58 That happens early, and always since then you have quite limited access to real hardware. 13:39:38 As for using "bare metal", I wonder what runs operating system then if not "bare metal"? 13:40:32 We have all those libraries exactly to simplify things by reusing what was written before. 13:43:08 CM is stuck in sixties with his "POL" book and his understanding of how software engineering works. 13:59:33 --- join: BlueSmoke999 (~HumanBot@dsl-vlan429-66-18-205-203.broadband.nucleus.com) joined #forth 14:08:49 --- join: kumool (~mool@adsl-64-237-224-74.prtc.net) joined #forth 14:11:00 --- quit: kumul (Ping timeout: 240 seconds) 14:11:58 --- join: ASau` (~user@p54AFE18E.dip0.t-ipconnect.de) joined #forth 14:13:55 --- quit: BlueSmoke999 (Quit: Relax, its only ONES and ZEROS!) 14:14:54 --- quit: ASau (Ping timeout: 245 seconds) 14:22:05 --- nick: ASau` -> ASau 14:30:48 --- quit: aranhoide (Ping timeout: 264 seconds) 14:49:45 --- join: nys (~nysnamovo@blk-142-60-139.eastlink.ca) joined #forth 15:06:43 --- join: aranhoide (~smuxi@0.Red-83-59-7.dynamicIP.rima-tde.net) joined #forth 16:39:31 --- quit: jyc (Quit: ZNC - http://znc.in) 16:41:13 --- join: jyc (~jyc@173.245.6.163) joined #forth 16:51:34 --- join: Bahman (~Bahman@2.146.211.149) joined #forth 16:57:14 --- quit: karswell` (Read error: Connection reset by peer) 17:23:04 --- quit: daowee (Read error: Connection reset by peer) 19:55:58 --- quit: nys (Quit: quit) 20:24:54 --- quit: LinearInterpol (Ping timeout: 240 seconds) 20:33:19 --- quit: kumool (Ping timeout: 264 seconds) 20:39:18 --- join: bjorkintosh (~bjork@ip68-13-229-200.ok.ok.cox.net) joined #forth 20:41:16 --- join: kumul (~mool@67.224.178.69) joined #forth 20:48:26 --- join: true-grue (~quassel@95-26-152-139.broadband.corbina.ru) joined #forth 21:06:19 --- quit: bjorkintosh (Remote host closed the connection) 21:11:21 --- join: emocakes (~emocakes@124-168-52-63.dyn.iinet.net.au) joined #forth 21:13:25 --- join: foucist (~foobala@c-50-178-193-111.hsd1.in.comcast.net) joined #forth 21:13:30 foucist 21:13:32 welcome back 21:14:13 --- mode: ChanServ set +o foucist 21:14:29 --- mode: foucist set -o foucist 21:15:33 --- part: foucist left #forth 21:27:02 --- part: emocakes left #forth 21:50:28 --- join: asie (~textual@178235038113.elblag.vectranet.pl) joined #forth 22:01:01 --- quit: Bahman (Quit: Leaving.) 22:01:38 --- join: bjorkintosh (~bjork@ip68-13-229-200.ok.ok.cox.net) joined #forth 22:03:06 --- quit: aranhoide (Ping timeout: 246 seconds) 22:06:18 --- quit: kumul (Read error: Connection reset by peer) 22:06:53 --- join: aranhoide (~smuxi@177.Red-81-33-60.dynamicIP.rima-tde.net) joined #forth 22:23:57 --- quit: asie (Quit: I'll probably come back in either 20 minutes or 8 hours.) 23:59:59 --- log: ended forth/13.12.02