00:00:00 --- log: started forth/10.02.24 01:01:57 --- quit: nighty__ (Quit: Disappears in a puff of smoke) 02:26:45 --- join: dinya_ (~Denis@94.51.201.34) joined #forth 02:37:36 --- join: nighty__ (~nighty@210.188.173.245) joined #forth 02:57:42 --- quit: scj (Ping timeout: 276 seconds) 03:25:56 --- quit: I440r (Quit: Leaving) 03:55:22 --- join: scj (syljo361@boneym.mtveurope.org) joined #forth 04:02:28 --- quit: nighty__ (Quit: Disappears in a puff of smoke) 04:51:56 --- quit: kar8nga (Remote host closed the connection) 06:07:09 --- quit: gogonkt (Quit: leaving) 06:07:40 --- join: gogonkt (~info@59.38.200.134) joined #forth 06:09:45 --- quit: Deformative (Ping timeout: 245 seconds) 06:19:40 --- join: Deformative (~joe@141.212.202.249) joined #forth 06:38:53 --- quit: crc (Ping timeout: 246 seconds) 06:41:15 --- join: crc2 (~charlesch@c-68-80-139-0.hsd1.pa.comcast.net) joined #forth 06:45:10 --- quit: dinya_ (Ping timeout: 245 seconds) 07:07:14 --- quit: Deformative (Ping timeout: 246 seconds) 07:11:43 --- join: crc (~d8012b82@gateway/web/freenode/x-mcqwedjqjewkymcs) joined #forth 07:32:34 --- join: qFox (~C00K13S@5356B263.cable.casema.nl) joined #forth 07:52:54 --- join: kar8nga (~kar8nga@jol13-1-82-66-176-74.fbx.proxad.net) joined #forth 08:22:09 Hmmm. I decided I'm not putting any literal parameters in my instruction stream. Complicates the sequencer too much. 08:23:51 Instead I will have my LIT instruction (which previously meant that the 16-bit literal value would "appear shortly" in the instruction stream) will push zero to the stack and set a bit in the ALU. 08:24:46 When that bit is set, five-bit opcodes will no longer have their usual meaning. Instead, each five bit pattern will cause the ALU to left-shift the stack top by four bits and set the vacated low-order four bits to the low order four bits of the five-bit instruction pattern. 08:25:26 As long as the most significant bit of the instruction pattern is zero the "literal bit" will remain set. The last five-bit pattern meant to be intepreted this way will have its most significant bit set. That will clear the literal bit. 08:25:29 how many system gates on the fpga do you think it will need? 08:26:01 I don't know yet, but not many. The sequencer itself is very, very simple. 08:26:29 I don't have a good feel for how big the ALU will get. Sort of depends on how fancy I want to get with things like barrel shifters and so forth. 08:26:58 Jump instructions were also going to expect 16-bit inline parameters for the target, but I'm going to make all of them take their target from the stack. 08:27:35 That way I can use the mechanism just described to put that value on the stack and then just execute JUMP, CALL (for computed calls), or whatever. 08:28:09 So the instructions stream will contain 16-bit cells that have only two possible meanings: a nested colan definition call (MSB=0) or three five-bit opcodes (MSB=1). 08:28:24 because I was looking at some actel igloo nano fpgas, they're small, cheap and power efficient. 30K gates for €4 08:29:02 One clock cycle for nesting to a new colan definition, one clock cycle for returns, and as long as we're processing primitives they'll all execute one per clock cycle too, with no overhead. 08:29:19 100 MHz should be easy - We might manage 200. 08:29:27 On a Spartan 6. 08:29:41 Maybe not quite that fast on earlier generations. 08:29:56 I'll let you know how big it is as soon as I know. 08:30:03 cool 08:31:21 I actually like this literal scheme; it will save space because an awful lot of literals in programs are small integers. For literals 0-15 this will take just 10 bits of instruction space, whereas the "inline parameter" method would alwyas have taken 21, no matter the value of the literal. 08:32:08 This scheme will take 25 worst case (LIT + four additional 5-bit chunks to build up a full 16-bit literal). 08:33:14 Only if you need bits in the top nibble will this scheme take more space than the other one. 08:33:22 --- join: Deformative (~joe@bursley-183118.reshall.umich.edu) joined #forth 08:33:59 Small negative numbers, though, do have bits in the top nibble. Hmmm, wonder if I should have "LIT+" and "LIT-" instructions to specify in advance whether the intended result was positive or negative? 08:35:03 I don't expect to run out of opcodes, LIT+ would push 0 to the stack top; LIT- would push -1. 08:35:22 The rest would work the same; I'd let the compiler figure out what the proper data nibbles should be. 08:38:05 Hey Kip. 08:48:15 --- join: GeDaMo (~gedamo@dyn-62-56-89-110.dslaccess.co.uk) joined #forth 08:48:27 Hi Joe. How goes? 08:58:34 Ok so far. 08:58:41 The interview with Cisco was.. Interesting. 09:04:14 scj: the igloo nano fpga's look interesting. thanks for mentioning them 09:09:24 Igloo is a cool family. 09:09:41 I've never used it, but we were looking hard at it before I left the "job before this one." 09:10:21 What do you guys program your fpgas with? 09:10:23 Verilog? 09:12:52 --- join: ASau (~user@83.69.227.32) joined #forth 09:16:06 A mixture of schematics and VHDL. 09:17:47 I'm sort of old school; whether via schematic or VHDL I like to specify my design at a very low level; explicitly calling out functional blocks and "wiring them together." My primary FPGA engineer, though, prefers to use a more behavioral approach and let the synthesizer take down to the metal. 09:19:01 I like to know *exactly* what's going on inside the thing. 09:19:52 I think in terms of registers, muxes, state machines (usually one hot; simplifies the equations) and so on. 09:19:55 Why can't you do that in verilog? 09:20:14 You can; VHDL and Verilog are just two flavors of the same kind of thing. 09:20:20 Like Baptist and Methodist. ;-) 09:20:36 Hmm. 09:20:37 VHDL just took root around here. 09:20:44 I see. 09:26:42 --- quit: kar8nga (Ping timeout: 256 seconds) 09:39:27 --- join: kar8nga (~kar8nga@jol13-1-82-66-176-74.fbx.proxad.net) joined #forth 09:39:29 --- quit: kar8nga (Client Quit) 09:40:40 --- join: Maki (~Maki@dynamic-78-30-167-37.adsl.eunet.rs) joined #forth 09:46:15 --- join: kar8nga (~kar8nga@jol13-1-82-66-176-74.fbx.proxad.net) joined #forth 09:46:18 --- quit: kar8nga (Client Quit) 09:55:22 "Like Baptist and Methodist" suggests both are heresy :D 09:55:29 --- join: nizchka (~nizchka@h59237.upc-h.chello.nl) joined #forth 10:05:27 --- join: kar8nga (~kar8nga@jol13-1-82-66-176-74.fbx.proxad.net) joined #forth 10:05:30 --- quit: kar8nga (Client Quit) 10:06:50 --- quit: nizchka (Ping timeout: 265 seconds) 10:15:26 --- join: nizchka (~nizchka@h59237.upc-h.chello.nl) joined #forth 10:25:28 --- quit: nizchka (Ping timeout: 245 seconds) 10:44:46 --- join: nizchka (~nizchka@h59237.upc-h.chello.nl) joined #forth 10:51:54 --- quit: crc (Ping timeout: 252 seconds) 11:37:43 --- quit: qFox (Quit: Time for cookies!) 11:40:43 --- join: qFox (~C00K13S@5356B263.cable.casema.nl) joined #forth 11:51:39 Cool; got that Spartan 6 development kit hooked up and working. Just running demos right now, but it looks like everything works right. 12:19:43 --- quit: nizchka (Remote host closed the connection) 12:48:13 --- quit: TreyB (Ping timeout: 260 seconds) 12:49:47 --- join: TreyB (~trey@adsl-99-165-169-187.dsl.hstntx.sbcglobal.net) joined #forth 13:06:32 --- quit: qFox (Quit: Time for cookies!) 13:06:35 KipIngram: thumbs up :) 13:49:34 --- join: tathi (~josh@dsl-216-227-91-166.fairpoint.net) joined #forth 13:49:51 --- quit: Maki (Quit: Leaving) 13:55:47 --- join: kar8nga (~kar8nga@jol13-1-82-66-176-74.fbx.proxad.net) joined #forth 13:55:50 --- quit: kar8nga (Client Quit) 14:12:46 --- quit: tathi (Read error: Connection reset by peer) 14:29:28 --- join: skas (~skas@eth488.act.adsl.internode.on.net) joined #forth 14:51:56 --- quit: GeDaMo (*.net *.split) 14:51:56 --- quit: crc2 (*.net *.split) 14:53:42 --- join: crc2 (~charlesch@c-68-80-139-0.hsd1.pa.comcast.net) joined #forth 15:00:01 --- join: I440r (~mark4@c-69-136-171-118.hsd1.in.comcast.net) joined #forth 15:06:42 --- quit: Deformative (Ping timeout: 256 seconds) 15:56:07 --- join: erider (~chatzilla@unaffiliated/erider) joined #forth 16:00:12 --- join: segher (~segher@84-105-60-153.cable.quicknet.nl) joined #forth 16:17:47 --- quit: erider (Remote host closed the connection) 16:41:03 --- join: Al2O3 (~Al2O3@c-75-70-11-191.hsd1.co.comcast.net) joined #forth 16:43:24 --- join: Deformative (~joe@bursley-183118.reshall.umich.edu) joined #forth 17:05:23 --- mode: ChanServ set +o crc2 17:05:28 --- nick: crc2 -> crc 18:09:13 --- quit: Deformative (Ping timeout: 264 seconds) 19:56:46 --- join: Deformative (~joe@bursley-183118.reshall.umich.edu) joined #forth 20:10:35 --- join: nighty__ (~nighty@210.188.173.245) joined #forth 22:34:17 --- quit: gnomon (Quit: powering down) 23:03:38 --- join: gnomon (~gnomon@CPE0022158a8221-CM000f9f776f96.cpe.net.cable.rogers.com) joined #forth 23:08:36 --- quit: skas (Quit: Leaving) 23:46:05 Deformative: JFYI, there is much more sense to store string length than to terminate line with sentry symbol. 23:46:39 Deformative: this very part is done in Forth way better than in C. 23:47:15 Deformative: crc is wrong there. 23:53:08 --- quit: ASau (Read error: Connection reset by peer) 23:54:46 --- join: ASau (~user@83.69.227.32) joined #forth 23:59:59 --- log: ended forth/10.02.24