00:00:00 --- log: started forth/05.03.13
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00:26:31 <Serg[GPRS]> hi !
00:27:04 <Serg[GPRS]> in FASM, can i define macro equal to instruction name, to redefin it hard way ?
00:27:38 <Serg[GPRS]> i need this for 2-stack idea
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08:44:53 <crc> Serg[GPRS]: yes, you can define macros equal to the instruction name in FASM
08:45:52 <Serg[GPRS]> aha, i found out, but considered it unwise and misleading for my purpose
08:46:11 <Serg[GPRS]> i have trubble w/ macros, may u help me ?
08:46:47 <crc> I'll try to
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10:31:43 <arke> : manage-sarray  ( id offset n size type link -- id offset' )
10:31:43 <arke>            store-link 0 ,  ,
10:31:43 <arke>            2 PICK ,   3 PICK ,
10:31:43 <arke>            TYPE-ID ,
10:31:43 <arke>            DUP ,
10:31:45 <arke>            *
10:31:47 <arke>            +
10:31:50 <arke>            \ reserve additional space for structure tag info
10:31:52 <arke>            2 CELLS +
10:31:55 <arke> ;
10:31:57 <arke> ugliest forth evar
10:34:06 <crc> what's that from?
10:34:38 <arke> some actual code from iTV
10:34:43 <arke> well, it was
10:34:47 <arke> before jeff fox went over it
10:34:47 <arke> :)
10:34:52 <arke> http://www.ultratechnology.com/structs.fth
10:35:03 <arke> 27K of forth source to implement C style structures
10:35:13 <crc> ick
10:35:14 <arke> I've coded it in a block in pygmyforth
10:36:04 <crc> :)
10:36:22 <arke> No joke :)
10:36:28 <arke> didn't have the late resolving crap
10:36:31 <arke> but it worked fine
10:36:44 <arke> I still have it, hold...
10:39:23 <arke> ( Structures )
10:39:24 <arke> : STRUCT ( -n) 0 ;
10:39:24 <arke> : F-ARRAY ( n#-n) CREATE OVER , + DOES> @ + ;
10:39:24 <arke> : F-WORD 2 F-ARRAY ;
10:39:24 <arke> : F-BYTE 1 F-ARRAY ;
10:39:26 <arke> : F-STRUCT ( na-n) F-ARRAY ;
10:39:29 <arke> : END-STRUCT CREATE , DOES> @ ;
10:39:31 <arke> : UNION ( a-an) 0 ;
10:39:34 <arke> : WITH ( an-anb) 0 ;
10:39:36 <arke> : END-UNION ( anb-a) MAX OVER , +  ;
10:39:39 <arke> I did that almost a year ago :)
10:39:50 <arke> structure + union, in 0 lines
10:39:52 <arke> 9*
10:39:53 <arke> :)
10:40:53 <arke> it was polymorphic too :D
10:41:02 <arke> for what i did
10:41:08 <arke> made a little crappy program for my cousin
10:41:17 <arke> you had a general struct
10:41:25 <arke> and you'd "cast" it
10:41:41 <arke> so STRUCT-NEXT would give you the link field
10:41:49 <arke> STRUCT-DATA the actual struct that this was casted to
10:41:50 <arke> ;)
10:43:19 <crc> that would work in retroforth if you had a definition for max :)
10:43:20 <crc> : struct : union : with 0 ;
10:43:20 <crc> : f-word 2 f-array : f-struct : f-array create over , + does> @ + ;
10:43:20 <crc> : f-byte 1 f-array ;
10:43:20 <crc> ' constant alias end-struct
10:43:21 <crc> : end-union max over , + ;
10:43:37 <crc> err, typo in the second line....
10:43:43 <crc> : f-word 2 : f-struct : f-array create over , + does> @ + ;
10:43:45 <crc> there
10:43:53 <arke> :D
10:44:55 <crc> structures and unions in 5 lines :)
10:45:16 <arke> :)
10:45:18 <crc> (I added does> back to retroforth, at least for now...)
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10:59:47 <Serg[GPRS]> re
11:00:24 <Serg[GPRS]> just tryed 'Playboy the mansion' game - good idea but crappy overwhelmed with tycoon strategy ;((
11:07:18 <qFox> try darwinia
11:07:22 <qFox> its a good game
11:07:33 <Serg[GPRS]> what's it ?
11:07:45 <qFox> proves that good games nowadays dont need a dvd full of images to be a great game
11:07:52 <qFox> its an rts, i guess
11:08:14 <I440r> a whole dvd full of sound and images does NOT make a good game... i totally agree
11:08:23 <I440r> 99% of all games have a play life of about 3 hours for me
11:08:27 <I440r> then its "bleh" 
11:08:28 <Serg[GPRS]> ble-e-e-etch, i can't play RTS coz my brain creeps apart between units
11:08:46 <I440r> on the other hand games like the original settlers i STILL play
11:08:48 <qFox> well, the whole game is about 30meg
11:09:05 <qFox> its a full 3d environment, using about 10 or so sprites
11:09:05 <qFox> :p
11:09:16 <qFox> tiny sprites, i might add
11:09:40 <Serg[GPRS]> hehe, STUNTS is 1 floppy and i still play it, coz dunno any game where i can build and run stunt tracks
11:10:30 <I440r> qfox what does it run on/under ?
11:10:34 <qFox> anything
11:10:41 <qFox> win 'nix mac
11:10:56 <qFox> from the makers of uplink, if you know that game
11:11:19 <qFox> although this is an entirely different game
11:11:26 <qFox> uplink was a good game as well
11:11:33 <Serg[GPRS]> if say about erotic game, i wanna one where i can wander all around open world (GTA like) and fu... everyone different ways, upgrading the skills like in Diablo ;)))
11:12:12 <qFox> go for it 
11:12:14 <qFox> :)
11:12:48 <qFox> i'm still wondering whether i'll try my modding skills at darwinia, you get the editor when you finish the game
11:12:54 <qFox> which is not a seriously hard challenge
11:13:31 <Serg[GPRS]> it gonna bust sparks out of CPU - even balance holding on arbitrary contact points is quite a challenge
11:17:48 <Serg[GPRS]> a friend of mine tryed to write 'mad positions generator' long ago - that sucked completely
11:18:56 <qFox> what does that do?
11:20:54 <Serg[GPRS]> random generator of sex positions ;)) he managed to cope with joints angles, but completely failed with hmm.... weight distribution
11:21:04 <qFox> haha
11:23:27 <Serg[GPRS]> we had a lot of LOL on it's ideas ;))
11:24:18 <Serg[GPRS]> much harder whan 'walking targets' in shooters ;))
11:26:43 * Serg[GPRS] dislikes to hold any balance at all ;)))
11:31:21 <Serg[GPRS]> yeah, i fall asnooze, bye !
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13:10:39 <slava_> any ppc experts: is blr the same as bclr?
13:10:56 <slava_> i'm finding powerpc assembly more complicated than x86
13:11:05 <slava_> and these simplified mnemonics are confusing as hell
13:11:47 <Frek> slava_: yes
13:11:54 <Frek> bclr with 20 as argument
13:11:59 <Frek> ie ALWAYS
13:12:27 <Frek> slava_: but if you see bclr it's extended mnemonics not simplified :)
13:12:51 <slava_> ok
13:13:19 <Frek> but basically all branches are conditional; bclr = branch conditionally to lr, if the condition is ALWAYS (or 20) it's always taken, so it's the samething as branch to lr 
13:13:41 <slava_> ok
13:14:25 <slava_> well, i've almost reached my goal for today, of being able to push values on the stack :)
13:14:56 <Frek> :)
13:15:43 <slava_> you know what's weird?
13:15:47 <slava_>   30:   4e 80 00 20     blr
13:15:51 <slava_> this is gcc-generated code
13:15:57 <slava_> that doesn't look like bclr 20 at all
13:16:05 <Frek> stack management is probably about the trickiest to learn when dealing with powerpc assembly, one can get a bit confused to start with as there's different concepts 
13:16:28 <slava_> well, i mean a forth stack. its pretty straightforward
13:16:29 <Frek> the red zone for example can be a bit confusing 
13:17:17 <Frek> slava_: it is 
13:17:44 <Frek> it's bclr 20,0 which is blr 
13:17:54 <slava_> ok
13:18:26 <Frek> the problem is that; I don't remember x86 asm very good though, but a opcode is exactly one byte on the x86 right ? 
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13:19:10 <slava_> well, 1 or 2
13:19:15 <Frek> on a powerpc it's 6 bits I think; could be 5 bits, I don't remember exactly 
13:19:47 <Frek> so unless you're really good with masking numbers by head; it can be difficult to figure out what instruction a certain hex sequence may be 
13:19:52 <Frek> however usually branches starts with 4 
13:20:03 <slava_> i have a .b word for that :)
13:24:45 <Frek> pretty simplified; that means if the 8 digit hex sequence starts with 0 it's a trap or similar, 1 it's multiply, 2 it's a compare, 3 it's an add/sub, 4 it's a branch, 5 it's rotate, 6 it's a or, 7 it's an and, 8 it's a load, 9 it's a store same with a/b (load store resp), c/d floating point instruction
13:25:02 <Frek> but that's generalized
13:25:40 <Frek> so 0x81212121 would be some form of load instruction
13:25:56 <Frek> 0x31212121 would be some form of add (subtract) instruction
13:26:00 <slava_> hmm
13:27:07 <Frek> that may be very vague, but it can give you a clue if you don't have an disassembler handy and just wanna verify some code you generated on the fly etc. 
13:27:29 <slava_> i use gdb :)
13:27:41 <Frek> works fine.
13:28:03 <Frek> but this may be quicker if not precise information is required
13:28:08 <Frek> -t
13:28:44 <Frek> so if you see for example "0x60000000" 
13:28:49 <Frek> you know it's an or :) 
13:29:08 <Frek> which is effectively the samething as an nop on the ppc :P
13:29:24 <Frek> or 0,0,0 
13:29:25 <Herkamire> conditionals are confusing on ppc
13:29:47 <Herkamire> but generally don't do much with them.
13:29:58 <Frek> I donno if they're confusing; the powerpc is just not suitable for "in head" disassembly 
13:33:17 <slava_> ok, finally i got blr working :)
13:33:43 <slava_> stw     r0,20(r1) <-- is this indexed addressing mode?
13:34:56 <Frek> no
13:35:17 <Frek> indexed has an x in the mnemonic 
13:35:26 <Frek> and takes 3 registers as arguments 
13:35:55 <Frek> lbzx r3,r4,r5 would be an indexed instruction for example
13:36:03 <slava_> ok
13:36:21 <slava_> in ppc terminology, is a 'word' 32 bits?
13:36:22 <slava_> or 16?
13:36:22 <Frek> where EA is calculated as the sum of r4 + r5 
13:36:27 <Frek> it's 32 bits, yes
13:36:29 <slava_> ok
13:37:06 <slava_> stw     r0,20(r1) stores the value at 20+r1 in r0?
13:37:55 <Frek> yes
13:37:58 <slava_> ok
13:37:59 <Frek> however r0 is a bit specific 
13:37:59 <arke> er?
13:38:03 <Frek> you can't use it like that 
13:38:04 <arke> isnt it the other way around?
13:38:09 <Frek> ah
13:38:10 <Frek> yea
13:38:12 <Frek> eh ya even
13:38:14 <arke> doesnt it store = in (20+r1)?
13:38:19 <Frek> stw stores contents of r0 
13:38:26 <slava_> ok
13:38:27 <arke> r0 is always 0
13:38:28 <arke> :)
13:38:42 <Frek> slava_: if it's been an lwz it's been as you said
13:39:18 <slava_> so swz and lwz are identical except the arguments are swapped?
13:39:39 <Frek> slava_: no the arguments are the same; it's just the functionality that's swapped :)
13:39:44 <slava_> ok
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13:41:12 <Frek> like lwz r3,0(r4) is store load contents of 0(r4) into r3, stw r3,0(r4) is store contents of r3 into 0(r4); the first parameter is always the source/destination/result  
13:41:27 <Frek> well destination = value you want to save 
13:41:33 <Frek> or register you want to load into 
13:42:05 <Frek> I donno exactly how to explain it better; it's not that complex; i'm just can't think of a better example right now 
13:42:28 <slava_> ok
13:43:19 <Frek> it's very similar to lwz r3,offset(r4) is like r3=r4[offset] in C, while stw r3,offset(r4) is r4[offset]=r3 ; I guess one can think of it as the arguments are swapped, but I donno
13:44:06 <slava_> ok, i got the stw opcode assembling
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13:46:59 <slava_> : PUSH-DS
13:46:59 <slava_>     #! Push r18 to the datastack.
13:46:59 <slava_>     14 14 4 ADDI
13:46:59 <slava_>     18 14 0 STW ;
13:47:02 <slava_> i think this is right :)
13:47:10 <slava_> lets see what gdb says
13:47:40 <slava_> 0x3202c0a4:     addi    r14,r14,4
13:47:40 <slava_> 0x3202c0a8:     stw     r18,0(r14)
13:47:45 <slava_> is this an ok way to do it?
13:48:20 <Frek> define "ok"
13:48:48 <slava_> "correct" :)
13:49:08 <Frek> it works; but it's far from an optimal way, also the stack pointer is usually kept in r1 on the powerpc; but it has no "technical" difference other than being coherent 
13:49:21 <slava_> what is a more optimal way?
13:49:24 <slava_> i don't want to take over r1
13:49:38 <Frek> a better way would be to store with the offset parameter 
13:49:49 <slava_> but i have to increment r14 anyway
13:49:57 <Frek> then increment/decrement the stackpointer when all values are stored 
13:50:04 <slava_> oh yes, i see what you mean
13:50:07 <Frek> now you're generating two instructions per store 
13:50:14 <Frek> instead of technically only one required.
13:50:25 <slava_> i'll get it working first, then optimize later :)
13:50:25 <Frek> but it can be tricky to do it another way :)
13:50:35 <Frek> yea, functionality is always the most important
13:51:07 <slava_> my x86 backend is a bit lame too, but over time both backends will do optimization
13:52:06 <Frek> well a lame backend is better than no backend :)
13:53:58 <slava_> does the instruction cache have to be flushed on powerpc?
13:55:17 <tathi> yes.
13:55:28 <tathi> well, flush the dcache, invalidate the icache.
13:55:54 * tathi goes to find the code
13:57:07 <Herkamire> I wouldn't use r1 for the stack
13:57:21 <Herkamire> C stuff uses it's stack differently than I do
13:57:49 <slava_> if i didn't have a C substrate i could use registers more optimally on both x86 and ppc
13:58:02 <slava_> eg, on x86 the ebp register is wasted due to C brain damage
13:58:11 <Herkamire> slava_: it's not really an optomization.
13:58:25 <Herkamire> just:   stwu r18, 4(r14)
13:58:46 <slava_> oh, that updates r14?
13:58:51 <Herkamire> yes
13:58:55 <slava_> thanks for the tip
13:59:03 <tathi> _before_ doing the store/load
13:59:22 <slava_> tathi, it doesn't matter in this case, though?
13:59:34 <Herkamire> so stwu r18, x(r14) will add x to r14, and store to that address (leaving x+r14 in r14)
13:59:49 <Herkamire> it's important to remember that it is before.
13:59:55 <Herkamire> there is no way to change the pointers after
14:00:02 <Herkamire> so your pop will be two instructions.
14:00:10 <Herkamire> pop would be:
14:00:11 <slava_> right
14:00:22 <Herkamire>    addi r14, r14, -4
14:00:45 <Herkamire> oops
14:00:52 <Herkamire> scratch that
14:00:54 <Herkamire>    lwz r18, 0(r14)
14:00:57 <Herkamire>    addi r14, r14, -4
14:01:11 <tathi> ok, a cache line is 32 bytes.
14:01:31 <tathi> for each cache line, do dcbf; sync; icbi
14:01:42 <tathi> and then end up with sync; isync
14:01:49 <Herkamire> you can have it so either push or pop is one instruction. and you can also choose if you want the stacks to go up or down.
14:02:13 <tathi> I do have some actual code if you'd like.
14:02:15 <slava_> i'm not sure either offers a clear benefit. i guess i push as often as i pop :)
14:02:44 <slava_> tathi, is there any way to flush the entire icache in one step?
14:03:00 <slava_> or indeed, does one have to do this before executing code that was just generated?
14:03:18 <tathi> AFAIK you have to do that
14:03:43 <Herkamire> it's not so bad if you remember to do it
14:04:11 <Herkamire> we just keep a pointer to where we've flushed to, and have a word that flushes from there to HERE, then updates the pointer
14:04:29 <tathi> mprotect +x under linux does it.
14:04:38 * slava_ ponders
14:06:06 <tathi> It is kind of a nuisance. :(
14:06:30 <slava_> do you have code that does this?
14:06:39 <tathi> yes.
14:07:12 <tathi> takes start/end addresses, computes how many cache lines and flushes them.
14:07:27 <slava_> gas syntax assembly?
14:07:53 <tathi> yes
14:07:59 <slava_> cool
14:08:06 <slava_> can you paste bin it please?
14:08:07 <tathi> that's the only free PPC assembler that I'm aware of, unfortunately.
14:08:13 <tathi> sure.
14:10:02 <tathi> http://paste.lisp.org/display/6575
14:10:42 <tathi> that's straight from my forth, so it assumes a couple of things.
14:11:03 <tathi> I could rewrite it to just take start/end addresses in r3/r4 (or whatever) easily enough.
14:11:21 <slava_> i'd need to call this from C, and my 'here' is compiled.here (compiled is a global struct)
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14:16:09 <slava_> any reason this code gives a segmentation fault?
14:16:10 <slava_> 0x3202c010:     stwu    r0,0(r14)
14:16:10 <slava_> 0x3202c014:     blr
14:16:48 <Frek> r14 is invalid ? 
14:16:58 <slava_> it shouldn't be
14:16:59 <slava_> let me check
14:18:51 <tathi> ok, posted new routine as annotation to the original paste
14:18:59 <slava_> ok
14:19:17 <slava_> thanks
14:23:30 <slava_> are you guys sure that r0 contains 0 ? :)
14:24:10 <tathi> where?
14:24:22 <slava_> somebody said this earlier todya
14:24:24 <slava_> it seems its not true :)
14:24:41 <tathi> oh, r0 isn't a truly general purpose register.
14:24:54 <tathi> for several instructions, a value of 0 means a literal 0 rather than register 0.
14:25:22 <tathi> first address register of indexed addressing, for instance.
14:25:39 <slava_> oh, ok
14:26:01 <tathi> and first source register for add immediate.
14:26:35 <tathi> li rA,LIT = addi rA,"r0",LIT
14:26:50 <slava_> ah! that's the source of my confusion
14:26:58 <slava_> so 'li' is not a real instruction either
14:27:02 <slava_> i was just looking for it :)
14:27:32 <Frek> slava_: no I said r0 is a special register; it can't be used all the time 
14:27:38 <slava_> k
14:27:47 <Frek> basically you just use r0 for temporary lr store 
14:27:55 <Frek> like mflr r0; ..... mtlr r0; blr; 
14:29:36 <tathi> Appendix F of that MPCFPE32.pdf is simplified mnemonics, though it doesn't have a short list of all of them.
14:32:12 <slava_> ok, i can push 16 bit literals on the stack :) :)
14:32:29 <tathi> :)
14:32:33 <slava_> what is the idiomatic way to push a 32 bit lit? li followed by an add with shift of some kind?
14:32:39 <slava_> s/push/store into a register/
14:33:00 <tathi> I use lis; ori
14:33:07 <slava_> ok
14:33:20 <slava_> lis ra,lit = adds ra,"r0",lit ?
14:33:20 <tathi> The idiomatic way (I think) is li; addis
14:33:28 <slava_> or sounds better than add :)
14:33:29 <tathi> addis, but yes
14:33:32 <slava_> ok
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14:34:10 <tathi> yeah, if you do li; addis; you have to adjust the high 16 sometimes because you loaded a _signed_ 16-bit immediate
14:34:24 <tathi> food, back later
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14:38:13 <slava_> hey eiz
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14:38:19 <slava_> i've been getting a lot of help in here :)
14:44:00 <TheBlueWizard> good :)
14:49:53 <tathi> amazing the concentration of PPC folks on this channel ;)
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18:22:52 <crc> goodnight
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19:59:56 --- quit: asymptote ("Free the mallocs!")
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23:59:59 --- log: ended forth/05.03.13