00:00:00 --- log: started forth/04.07.11 00:00:25 I like being able to compile machine instructions anywhere 00:00:29 So do I. 00:01:13 But when a simple + becomes four 32-bit instructions (even if it does effectively execute in a single cycle), the space-savings of a direct-threaded implementation becomes appealing. :-) 00:02:10 (well, that's an exaggeration; a + operation can be described in as little as 2 TTA instructions, provided the compiler is smart enough to optimize out the data stack manipulations that goes along with it.) 00:02:34 what's tta? 00:02:43 Transport Triggered Architecture 00:02:52 what's that? 00:03:08 It's a CPU architecture (relatively recent as of 1990) that works not by specifying operations, but by data flows. 00:03:48 For example, the PowerPC add r2, r3, r4 would be encoded like this in a TTA: 00:04:11 R3 -> add_o, R4 -> add_t ;; These two moves operate in a single cycle 00:04:28 add_r -> R2, ...etc... ;; This operates in the subsequent cycle. 00:04:50 what do O and T stabd fir? 00:05:05 add_o is the first operand register to the integer adder unit. 00:05:25 add_t is the second operand to the adder unit; however, writing to it also triggers (hence the _t) the adder to begin its work. 00:05:30 add_r is the result register. 00:05:36 i mean, is there a reason why they're called add_o and add_t instead of, say, add_o1 and add_o2? 00:05:44 Yes. 00:05:49 oh, nm i see now :) 00:05:55 I can write to add_o *all day long*, and the adder would never generate a result. 00:06:00 i typed too soon, sorry :) 00:06:07 :) 00:06:36 kc5tja: very cool 00:06:48 i hate this fucking patent business, though 00:06:48 (of course, in my design, I would make the adder an asynchronous unit, so changing either one would result in an addition result being generated. But for other things, like a multiplier, which is inherently pipelined, it's good to have a distinct trigger register.) 00:06:55 so each different math unit has it's own input regs that you copy operands to? 00:07:01 Yes. 00:07:13 and you can have any number of units, as long as you can fit them in the CPU's internal register space. 00:07:37 as long as you have room in your instructions to address that many registers 00:07:43 The number of (source, destination) pairs you can fit in a CPU instruction word determines how much data per cycle you can move around inside the CPU. 00:08:21 kc5tja: so with TTA you can do everything with just register copying? 00:08:26 Right. But you can play read-only and write-only register tricks (e.g., overlapping read-only and write-only registers to save space). 00:08:38 Herkamire: Yes. 00:08:46 fascinating 00:09:15 And there is no reason why all move-slots have to address the same set of registers either, or have the same number of bits. 00:09:37 TTA is just a concept, and it is proven to work. It's actually more powerful than VLIW. :D 00:10:16 could you move a cell directly from a result register in a unit to an operand register in a different unit? like moving the result of an addition directly to the address bus? or does everything have to go through an intermediate register set? 00:10:40 "same set of registers".... you mean like you could have a way to switch execution over to a different bank of registers? 00:10:46 Sonarman: Yes. This is one of its biggest advantages. There is reduced need for 32 general purpose registers because of this. Eight should be plenty. 00:11:27 ok, so if you have 16 registers, then you could have 8-bit instructions 00:11:39 4bits specifies source, 4bits for dest register 00:11:39 Herkamire: If you want. Usually different slots are hard-wired to different register banks. One architecture I've seen used slot 0 to manage the instruction pointer and return stack while slots 1, 2, and 3 were used for general purpose data processing. Made for some interesting programs. :) 00:12:17 slot, meaning which bits in a word the instruction is found in? 00:12:26 Right. Assuming you can fit the requirements with that. 00:12:31 Yes. 00:12:47 wow 00:13:09 For example, if I define a TTA that has 5-bit source and destination fields, then a (source, destination) pair is 10 bits wide. In a 32-bit word, I can fit 3 such pairs in at the same time, leaving two more bits left over for other uses. 00:13:42 and I think you were also saying this: there can be a different mapping from the source register bits in the instruction to actual register used, than the mapping of the destination bits to actual register 00:14:14 Another alternative would be to use that 8-bit slot for managing the instruction pointer and return stack, while leaving the remaining 24 bits available for two 6-bit-addressed register move operations. 00:15:14 Not generally recommended that happen, but yes, it is possible. For example, you'd like to think that add_t and add_o are write-only -- you already know what the operand values are, so why would you want to read from them? 00:15:35 Well, when an interrupt occurs, you'd like to be able to preserve the contents of the add_t/add_o registers, so you can restore them later on. :) 00:16:25 But then this opens up another possibility: if you have hardware interrupts disabled, and therefore no interrupt can occur guaranteed by the hardware, then the hardware can remap other read-only registers to add_t/add_o's space. :-) 00:16:29 sounds like a very cool architecture 00:16:31 So you can play all sorts of dirty tricks. :) 00:16:51 heh heh 00:16:58 makes perfect sense to me 00:17:10 It is a very cool concept. 00:17:22 writing could go to operands and GPRs 00:17:29 reading would go to results and GPRs 00:17:29 Writing software for one that actually runs efficiently and makes maximum use of all the available slots, now that is a harder question. 00:17:50 I don't even think it would be too confusing in many cases. 00:17:58 * kc5tja nods 00:18:09 eg if register 5.. when you write to it would be addition input, and read from it it would be addition result 00:18:32 it would appear that register 5 transforms a value you stick in there 00:18:36 I figure this: if I restrict my TTA's register set to only 32 registers, then switching contexts between tasks and/or interrupt handlers would be no more time consuming than it would be on an existing RISC. 00:19:11 interrupts are a bit too much for me to think about ATM 00:19:11 Yes, but as I've detailed above, you probably don't want to do that. 00:19:33 Instead, you'll want to overload the add_r (which IS read-only, no matter what). 00:20:18 right. because of interrupts 00:20:24 anyway, more questions :) 00:20:29 The nice thing about a TTA also is that it uses very, very little transistors. 00:20:29 :) 00:20:41 But unlike a stack processor, it does use more wires. 00:20:45 would it be easy to have concurrent executions of some of the moves specified in an instruction word? 00:21:03 Suppose I have a 32-bit word, with 3 10-bit slots. 00:21:19 Every clock cycle, assuming a memory fetch or store didn't occur, all three moves would occur in parallel. 00:21:42 This is a critical requirement for the TTA in order to compete with existing RISCs on code density and on speed. 00:23:14 oh, they always execute at the same time 00:23:18 Yes 00:23:42 so if one operation uses the results of another, they must be placed in seperate instruction words 00:23:52 That is correct, yes. 00:24:12 so would the stack be in memory for this architecture? 00:24:18 stacks 00:24:44 I would still have the stacks on-chip for this architecture, personally, for no other reason than to keep the bus free and clear. 00:25:00 cool 00:25:18 Unlike the stack architecture, the bus will ALWAYS be in use, since it can dispatch up to three move instructions per clock cycle. Lots of instruction traffic. 00:25:44 This means references to and from memory will be slow; 2 cycles instead of 1. 00:25:49 (except for instruction fetches) 00:26:13 wait 00:26:22 the bus is used in register moves? 00:26:24 Unless, that is, I use a Harvard architecture cache (split data and code cache). 00:26:37 or the bus is busy because you have to fetch an instruction word every cycle? 00:27:07 There would be four buses. The first bus talks to external memory, and attaches to the instruction register. Then there are the three *internal* buses which lets the internal registers talk to each other, under control of the instruction register. 00:27:44 Since one full 32-bit word gets executed per cycle, it needs to be refilled every clock tick. 00:27:58 (otherwise, the execution stalls until it's reloaded again.) 00:28:11 right 00:28:34 is it possible to fetch a data word and an instruction word the same cycle? 00:28:48 Herkamire: only with separate code and data caches. 00:29:16 If a unified cache is used, it would need to have twice as many read ports, which is actually more expensive than having split caches. 00:29:32 If there are no caches used, then no -- it'd have to arbitrate access to the bus, just like a DMA device would. 00:29:49 is this how you fetch from memory? -- move the address you want to fetch from into the address register. then (in the next instruction) move from another register (wherever fetches come in from the address register) 00:30:03 Yes. 00:30:35 you must have a seperate address register for soring, and fetching then right? 00:30:39 You could have the A register, which holds the address, and maybe MA and MA++ registers, both of which provide the fetched data, but one is a trigger to post-increment the A register. 00:30:52 Not necessarily. 00:31:06 Depends on what your requirements are when building the CPU. 00:31:30 oh, right, the fetch/store is triggered by asking for data _from_ the fetch-destination register (or store-source) 00:31:55 (or could be) instead of (as I was thinking) when you put the address in the address register 00:32:09 Actually, there are advantages to the latter. 00:32:24 that would have some advantages. like you could use the address more than once. 00:32:34 If you're working with slow memory (e.g., SDRAM), you can place an address in a dedicated fetch-address register, and then wait the required number of clock cycles before reading the fetch-data. 00:32:40 In the mean time, you could be doing other things. 00:32:52 right 00:33:04 I was thinking that a while back 00:33:40 So, clearly, while the stack architecture is clearly superior for the Kestrel, moving to the TTA is not a total loss, despite the code density issues. 00:34:42 oh, never mind. I was thinking it would be cool to have the trigger when you move from the fetch-destination, because then you could (eg) add something to the value, and store it back to the same location by moving your value to the store-source register 00:35:11 but it would be just as easy to change the value, and move the address from the fetch-address register to the store-address register 00:36:00 (I think you were talking about this before I understood much of it) 00:36:17 :) 00:36:19 seems to me there is a tough decision to make about how many bits each instruction within the word should have 00:36:42 if you make more small instructions, then you have more concurency, but each is more limited in what it can do. 00:37:01 I think TTAs work best when there is a separate code cache. This way, compact instructions can be pre-decoded into TTA sequences and stuffed into the (potentially much wider) internal code cache. 00:37:11 you must specialize so slots can do certain things. 00:37:44 Well, with dedicated stack units, I can approximate a single Forth operation in a single 32-bit word. 00:38:03 cool 00:38:08 I know for a fact that I can for +, -, AND, OR, XOR, COM, NEG, 2*, 2/, etc. 00:38:30 but with harvard architecture, you can't have your forth compile native code right? 00:39:05 Yeah, I can, but the cache system is more complex, because there is a separate instruction cache and a data cache. 00:39:25 So the CPU basically has two bus masters inside of it, and the bus interface unit has to constantly decide who to grant the bus to. 00:39:27 so there is some way to alter the code cache? 00:39:47 like PPC where you have to say that a certain block in the code cache is invalid 00:39:48 I would just do what other CPUs do, and have a means of invalidating code and data cache lines. 00:40:00 * kc5tja nods 00:40:40 I have to deal with the seperate caches in herkforth. 00:40:54 it seemed a bit complex to implement at first, 00:41:00 but I rarely think about it 00:41:23 * kc5tja nods 00:41:28 ; takes care of it 00:42:01 THEN has to flush the cache for the instruction IF compiled 00:42:09 How does ; know where the beginning of a word starts? Is that just a state variable somewhere? 00:42:44 I keep a value that is the highest address that has been flushed (wherever HERE was last time I called flush) 00:42:58 the flush routine flushes from there to HERE, and updates the value to the current value of HERE 00:42:58 Gotcha. 00:43:26 That makes perfect sense. 00:43:38 that works for everything except THEN which must flush a particular address, which could well been flushed already 00:44:00 eg like so: if drop ; then 00:44:07 But as long as IF and THEN appear in the same definition, wouldn't ; take care of it? 00:44:13 AHH. 00:44:15 Gotcha. 00:44:23 I do that a lot 00:44:25 no else 00:44:30 Likewise. :) 00:44:55 In fact, in my target compiler, I don't even have any support for interactivity, so I don't bother defining any new interpreters or compiler loops. 00:45:19 ': foo blah blah prim, prim, prim, blah blah ;' <-- all is *interpreted* directly by gforth. 00:45:43 foo is defined by ': using CREATE and DOES>. :D 00:45:51 huh? 00:46:06 ': does not enter a distinct "compile mode." 00:46:34 All it does is creates the word in gforth's dictionary, makes sure all the addresses are properly aligned, and initializes the tail-call optimization state variables. 00:46:37 That's it. 00:46:40 I can do stuff like: 00:46:48 ': foo 3 4 + . ;' 00:46:55 and it will literally print 7 to the screen. 00:47:03 Mean while, foo will just be composed of a return instruction. 00:47:34 why? 00:47:38 do you want it that way? 00:47:43 Because it takes only 50 lines of code to do it that way. 00:48:29 It's trivially simple to implement, and while inconvenient for the programmer, it's also very fast. 00:48:36 Note also that this is a cross-compiler/assembler. 00:48:50 I don't get it. how do you compile code or make definitions? 00:49:02 I just said, 'foo' is defined with CREATE and DOES>. 00:49:12 : ': create DOES> @ call, ; 00:49:38 So when foo is invoked, it compiles a call instruction to the word's target address. 00:49:52 (which is stored in the word's parameter field by ) 00:50:40 I'm too tired 00:50:53 Herkamire: Download my code, and study it. that's the only way to see the big picture. 00:51:02 kc5tja: ok. 00:51:10 right now I gotta go to bed though 00:51:14 should have 2 hours ago 00:51:17 It's how Chuck Moore implemented his first MachineForth compiler. 00:51:25 :) 00:51:31 Okies. I should too. 00:51:31 :) 00:51:34 Night! 00:51:41 --- quit: kc5tja ("THX QSO ES 73 DE KC5TJA/6 CL ES QRT AR SK") 00:51:57 --- quit: Sonarman ("leaving") 00:52:01 --- quit: Herkamire ("bed") 01:14:08 * Tomasu is away: dlrrp 01:20:50 --- quit: skylan (Remote closed the connection) 01:21:13 --- join: skylan (~sjh@vickesh01-4466.tbaytel.net) joined #forth 02:08:11 --- join: qFox (C00K13S@cp12172-a.roose1.nb.home.nl) joined #forth 02:33:09 --- quit: aum () 03:36:54 --- join: crc (crc@0-1pool176-5.nas6.philadelphia1.pa.us.da.qwest.net) joined #forth 03:55:08 --- quit: foobar (Read error: 110 (Connection timed out)) 05:08:17 --- quit: crc (Client Quit) 08:37:36 anyone awake ? 08:41:32 no 08:41:36 i meran 08:41:39 i mean 08:41:40 yes. 08:44:00 lol 08:44:05 make yer mind up :P 08:44:32 hm 08:44:55 hard to do. just got home from repainting the stairs, and cleaning up the rest of the house 08:45:09 Hi 08:45:10 my mind says yes, my body says no...thing 08:45:25 ahwell 08:45:27 sup? 08:45:27 :) 08:45:44 It's amazing how many serious bugs that can be hidden in a Forth that looks like it's working fine. 08:46:05 you mean like a hidden 2 stack depth initialization at boot? ;) 08:46:26 Nah, worse 08:46:32 like? 08:46:56 The doconstant word being completely wrong? :P 08:46:58 well i KNEW robert would be awake :P 08:47:02 hah 08:47:17 which forth ? 08:47:26 The DOS forth I discovered. 08:47:32 named ? 08:47:35 tforth 08:47:38 url ? 08:47:44 Hah, forget it :P 08:47:49 lol 08:47:51 Not until I fix the bugs. 08:47:58 It's kinda neat though. 08:48:04 you discoverd or created ? 08:48:06 * qFox passes it on to I440r behind his back 08:48:07 Just have to find this one bug... 08:48:09 I440r: Both :) 08:48:11 psst. 08:48:13 lol 08:48:16 hehe 08:48:17 thanx 08:48:25 It's on robert.zizi.org/tforth.html 08:48:28 * I440r looks at roberts code and lafs 08:48:32 But that version DOES contain a lot of bugs. 08:48:33 Bah 08:48:40 I stole most of it from you 08:48:44 rofl 08:48:44 So don't laugh too much :P 08:48:47 hehe 08:48:49 thief! 08:48:58 :P 08:49:05 maybe we should create a forht development page 08:49:09 you do know that i already ported isforth to dos right? 08:49:09 like 08:49:13 not for one forth 08:49:14 totally unreleased tho :) 08:49:19 I440r: Neat. :) 08:49:21 but with subpages for each forth 08:49:28 I440r: Well, this one is a little bit smaller ;) 08:49:29 like a sourceforge type of page 08:49:35 (and others...) 08:49:50 but then just for forth(ish) development 08:50:12 I guess we could use the forthfreak.net wiki for that. 08:50:38 hm no i think a wiki is not sufficient 08:51:32 * Robert thinks about floating-point numbers. 08:51:41 dont 08:51:41 If I only had some code to read/print those. 08:51:43 hehe 08:51:44 :D 08:51:53 I know they're not 60s enough for you, qFox 08:51:57 i dont even want to think about the float set myself 08:52:10 oh no, i'll have the float set 08:52:31 they are needed in a programming language, no doubt 08:52:38 or should be available anyways 08:56:15 i think i HAVE figured out how to do it though. create words in F that do primitive actions (mostly fetch store operations, and the +-/* AND OR XOR words), and compile the xt of those words and create a word in my new forth, that calls F's execute 08:57:09 that will prohibit the user to use any other lowlevel code (unless these words are added before my forth starts), but i dont think that'll be a problem 09:10:11 --- join: Herkamire (~jason@h000094d30ba2.ne.client2.attbi.com) joined #forth 09:47:27 anyone interested in seeing my 8051 forth ? 09:47:41 --- join: kc5tja (~kc5tja@66-74-218-202.san.rr.com) joined #forth 09:47:47 --- mode: ChanServ set +o kc5tja 09:50:04 kc5 wanna see my 8051 forth ? 09:50:25 i just put the tar.gz for it on isforth.clss.net under the 8051 link 09:50:51 * kc5tja nods 09:51:08 I still want to know how to get around PTSC's patent. 09:51:50 My TTA design will work (assuming there are no TTA patents -- however, I can't find any), but it'll pop 32-bit wide instructions faster than a rock star pops pills. 09:54:04 heh i gotta go. 09:54:07 bbl tho 09:54:23 ok 10:04:26 I fiddled with the recursive fib in herkforth some more. made an asm word just for it. 10:04:31 down to 5secconds 10:04:47 gcc with optomizations on was 6.8 10:05:33 I think the only difference between the code generated by herkforth, and what I would code in asm by hand, is that I would swap two instructions for better timing 10:06:00 * kc5tja nods 10:06:44 Herkamire: Nice. :) 10:07:01 Herkamire: What kind of threading/optimization/etc. does HerkForth do? 10:09:30 (!!) 10:09:46 Herkamire: I'm not too sure on this, but I think I just figured a way to work around the patent issue. 10:09:53 Keep the current, dense instruction encoding. 10:09:56 kc5tja: cool! 10:10:21 But, internal to the chip, have an instruction pre-decoder that translates the MISC opcodes into equivalent TTA operations, which are then executed by the TTA core. 10:10:23 Robert: it compiles native code. 10:10:51 Robert: not a whole lot of optomization, but I did a few tricks to see what it would take to beat/match gcc 10:11:03 It adds lots of transistors to the design, and almost certainly requires pipelining to work right, so I'm not sure how much of a performance gain I'd get. 10:11:49 Herkamire: OK, cool. :) 10:11:56 kc5tja: cool idea 10:12:36 What patent is it that you have to get around? 10:12:49 But the instruction pre-decoder can recognize certain instruction pairs, and do math between the functional units without ever touching the data stack, for example. Thus, it should at least compare to a regular MISC in overall performance. 10:13:15 U.S. 5,809,336 10:13:18 cool 10:13:44 What, "the use of numbers above three" ? 10:13:54 * Robert wonders if everything can be patented. 10:14:14 Robert: PTSC has a valid patent. It's a hardware patent. 10:14:29 And it seems MISC is obvious to us NOW, but back in 1992/1993, it wasn't. 10:15:11 lets patent de dot on the i! 10:15:13 Is the patent about MISC itself? Or some technical detail? 10:15:40 It describes the Patriot Scientific ShBoom! processor, which is the world's first MISC CPU. 10:15:52 dont patents run out after 5 years? 10:15:59 qFox: 5? You mean 20, right? 10:16:04 yes 10:16:05 :p 10:16:16 [19:15:51] dont patents run out after 20 years? 10:16:22 see 10:16:42 kc5tja: But isn't the patent limited to that processor? Or can't you do anything that even somewhat reminds of it? 10:16:52 --- join: foobar_ (fooboo@dialup-4.153.64.167.Dial1.Atlanta1.Level3.net) joined #forth 10:16:54 That patent was filed and granted in 1995, so that means it will expire no later than 2015. 10:17:42 The patent describes a processor of a particular architecture. 10:18:00 The ShBoom!'s internal architecture is used for illustrations, but c'mon -- MISC is MISC is MISC. 10:18:28 The only reason RISC took off is because all the initial RISC initiatives were funded with public funds! I can make a MIPS-I clone tomorrow if I wanted to, with absolutely no fear of legal retribution. 10:18:39 MISC was created under private investment capital -- it has every right to be patented. 10:18:57 Hehe. The question is, will they send a hitman after you if you make a hobby kit with a MISC processor? 10:19:19 I don't think that patent benifics society 10:20:08 Patents are meant to benefit their holders. :) 10:20:23 the patent system is meant to benifit society 10:20:26 Robert: No, *IF* I don't sell processors made with the design. I can sell my kits so that it uses my processor, and I can sell the blank FPGA and FPGA ROM for it, but you'll have to program the CPU yourself with only publicly available documents. 10:20:33 To be perfectly legal, that is. 10:21:04 Actually, patents benefit only their holders. 10:21:16 The whole concept of intellectual property is *fundamentally* flawed. 10:21:31 The notion that an *idea* can be controlled is total rubbish. 10:21:38 kc5tja: Can't you just ask them for permission? 10:21:49 the idea is, that patents encourage people to invent (ie big companies to pay inventors to spend time designing stuff) 10:21:51 that'll cost you blingbling 10:21:55 It creates a *false* scarcity in a capitalist society, and we know what those can do just by watching the whole dot-com bust. 10:22:03 and this benifits the world because their ideas are published. 10:22:03 kc5tja: I mean, it should be worth a try, as you won't exactly be a serious concurrent. 10:22:15 but in reality, it's usually used to stop people from using technologies at all 10:22:23 except sometimes big companies. 10:22:33 I say huge companies don't need any more help from the government 10:22:41 Robert: Certainly. And I will probably try to contact them on clarifying their position relative to little people like me. 10:22:54 i began to question patents when they started giving patents for software 10:23:25 there's even a patent on entertaining your cat with a laser pointer 10:23:27 Herkamire: PTSC has . . . 7 employees. They are suffering from millions of dollars in losses for at least the last four fiscal quarters. They are not a big company. :-) 10:23:33 foobar_: Haha. 10:23:42 Oh, *AND* Intel is suing *them* because of their recent lawsuits based on the patent. 10:23:55 kc5tja: oh, so they better start suing people 10:24:19 Such a mess. 10:24:20 If PTSC had placed their charges against Intel when they released the 486DX2, then they probably would have been in a much better position. 10:24:45 I meant big companies can sometimes use other people's patents (because they can afford the layers and licensing fees, or they can snag the patent holder with cross licensing or something) 10:25:03 * kc5tja nods 10:26:36 the public is starting to think that the point of patents and copyrights is so you can make money 10:27:07 and they think it's ok 10:27:13 fair even 10:27:26 this is patented: r = (v ^ (v >> (sizeof(int) * 8 - 1))) - (v >> (sizeof(int) * 8 - 1)); 10:27:54 and its purpose is...? 10:28:15 absolute value 10:28:18 without branching 10:28:19 --- join: SDO (~SDO@67-23-111-213.clspco.adelphia.net) joined #forth 10:28:25 ah 10:28:31 Who's the owner? 10:28:49 And, uh, I have a hard time to believe that is patented. 10:28:55 Vladimir Yu Volkonsky and assigned to Sun Microsystems . 10:29:09 Not even a brain-dead monkey would allow that to be patented. 10:29:09 are you able to patent math stuff? they are basically the same as a algorithm 10:29:44 according to the bit twiddling page at stanford 10:29:49 what's ^ do again? 10:29:54 I don't accuse all government officials of being intelligent, but I doubt they'd go THAT low. 10:29:57 xor 10:30:46 they patented patented playing with your cat 10:31:28 see 5,443,036) 10:31:37 I don't want to know. 10:31:59 FedGov is worse than a brain dead monkey 10:32:57 Herkamire: That's the whole point of the patent system. The whole "inventors benefit" business is bullshit. A patent is a license to a monopoly for 17 to 20 years, depending on the conditions under which it has been filed. 10:33:15 The laws behind patents are specifically tailored, and always have been, to benefit corporations. 10:33:23 --- part: foobar_ left #forth 10:33:28 --- join: foobar_ (fooboo@dialup-4.153.64.167.Dial1.Atlanta1.Level3.net) joined #forth 10:33:37 right. people buy the "inventors benifit" thing 10:34:16 software patents will not make any more jobs for programmers, or get programmers payed any more 10:34:20 * Tomasu is back (gone 09:20:13) 10:34:27 no. It will kill jobs. 10:34:30 they will just shift even more power to software giants 10:34:44 give them more power to sue anybody they want 10:34:58 i heard that the old Amiga had to pay the patent-holder for displaying a cursor 10:35:22 stuff like that is holding this computer business back imo :( 10:36:04 it's holding most businesses back 10:36:15 foobar_: No, but they did have to pay a patent holder for using XOR to draw things to the screen (which, I'd like to point out, I'm also doing. And they can fucking shove it.) 10:36:18 the automobile industry comes to mind 10:37:25 kc5tja: techniques that any good programmer would re-invent! 10:37:37 foobar_: And have, time and time agan. 10:37:40 again 10:37:59 that's the problem with patents. It makes it so people aren't allowed to invent things 10:38:13 Or even to just re-use things. 10:38:37 copyright law sucks in a lot of aspects, but it doesn't allow anybody to sue you for creating something you invented in your own basement 10:38:41 That was the original "public view" intent of patents: if I can't use XOR to draw a blob to the screen, I need to "invent" an alternative. 10:38:55 --- join: crc (crc@0-1pool88-84.nas48.philadelphia1.pa.us.da.qwest.net) joined #forth 10:38:58 Herkamire: Actually, yes it does. 10:39:19 kc5tja: how? 10:39:37 Herkamire: Patent law doesn't give a company to sue for something you independently invent, since patent documents are public documents anyway. Patent law only prevents you from (a) claiming it as your own, and (b) reselling manifestations without license. 10:40:03 Herkamire: Read DMCA, and the WIPO regulations that are currently being debated will only tighten the stranglehold. 10:40:15 As worded, WIPO's rules literally forbid a person to own a computer. 10:41:25 how do they do that? 10:41:34 money is power 10:41:52 They press charges against you, they have lawyers who know how to selectively interpret texts, and they can own you. 10:41:55 Simple as that. 10:42:02 and look at the absolute retards we elect to office 10:42:28 our court system doesn't work 10:42:47 Our court system does work, as long as the jury isn't bribed. 10:43:12 as long as you have $250,000 to spend on the case, which you don't get back even if you win 10:43:19 Like Microsoft did to Janet Reno. i'm still pissed off about that. 10:43:32 Herkamire: right 10:43:38 kc5tja: What did they do? 10:44:39 Herkamire: a prosecutor can destroy you even if you're innocent 10:45:02 Robert: Microsoft -- found guilty of EVERY anti-trust law we have -- gets off the hook by "donating" thousands of copies of Windows to needy schools (thus further indoctorinating thousands of kids on the Windows concept of computing). AT&T, however, which was found guilty of only a select few of our anti-trust laws, had undergone a *violent* and government-enforced corporate breakup. 10:45:09 Now, what the **FUCK** is wrong with this picture? 10:46:08 Heh. 10:46:13 Billy Gates is a thug who wants a monoply 10:46:19 wants? 10:46:23 how about has? 10:46:24 oh yeah that janet. the name rang a bell 10:46:42 It's nice how you can donate something that is free. 10:46:57 windows isn't free 10:47:08 Windows costs about $200 per license. 10:47:10 it's way more expensive, and way worse than something that is free 10:47:14 i wonder, is it really bill, the guy? or is he by now nothing more then a puppet controlled by the board of directors (or whatever is actually leading MS...) 10:47:20 It won't cost them any significant amount to give it away. 10:47:28 qFox: Bill *is* on the BOD. 10:47:33 i mean, bill has more cash then he could possibly spend in his next 50 lifes.. 10:47:36 qFox: gates controlls microsoft 10:47:39

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