00:00:00 --- log: started forth/04.05.09 00:20:20 --- join: [aXe] (~axe@pcp03956119pcs.sarast01.fl.comcast.net) joined #forth 00:20:21 --- quit: [-aXe-] (Read error: 104 (Connection reset by peer)) 00:59:19 --- quit: kc5tja ("THX QSO ES 73 DE KC5TJA/6 CL ES QRT AR SK") 01:02:59 --- join: Serg (~knoppix@193.201.231.126) joined #forth 01:19:09 hi serg 01:19:11 --- quit: [aXe] (Read error: 104 (Connection reset by peer)) 01:19:14 --- join: [aXe] (~axe@pcp03956119pcs.sarast01.fl.comcast.net) joined #forth 01:19:24 heya-a-a! 01:20:02 how's your work, forth etc... ? 01:20:59 i just bought an air rifle w/ optical sight ;) so i hit twice farther than w/ open sight 01:26:37 --- join: crc (~Charles_C@0-1pool176-7.nas6.philadelphia1.pa.us.da.qwest.net) joined #forth 01:33:56 heh 01:34:26 im working on the web page for isforth compliant with the spec 01:34:30 got most of it done 01:34:43 4.5 mm cal., 170 m/s by papers, 4x34 sight 01:34:58 nice 01:35:12 cool 01:35:28 i'm split-minded about isForth 01:35:50 from one point, i seem it conceptually ze best of Linux ones i tryed 01:37:04 but from another side, it's way fat, unstandard, hmm... 01:38:31 the fat will become more potional when i can metacompile 01:38:41 also, alot of the fat is VERY VERY usefull 01:38:53 but unless you know its there and how to use it its useless to you 01:39:00 which is where my present task comes in 01:39:05 documenting it all 01:39:06 sure ! 01:39:36 i think you do Forth for yourself, not for community... 01:39:41 plus i dont consider a 50k executable that can do everything isforth does to be fat :) 01:39:46 both 01:39:59 ull see, when isforth can do everything i want it to be able to do.... 01:40:30 unstandart features hit portability both of coder's skills and source codes 01:41:13 who cares about portability? 01:41:21 this is already locked on x86 AND on linux 01:41:51 and i dont give a flying fsck about producing anything thats portable because its a comlete and utter MYTH anyway 01:41:53 :) 01:42:26 myth ? no, you da-a-amn wrong ! 01:43:03 i test Perl script on Windoze and then send to provider's FreeBSD and it does exatly what i want ;)) 01:43:37 theres no such thing as portable code. any time you show me portable code ill show you lots of red tape visual clutter glue conditional compilation 01:44:10 what you realy have is 284765928456982 different versions of the same thing with the sources to all those versions interleaved into a totally unreadable BLOB within the same source files 01:44:23 isforth does not and will NEVER support conditional compilation 01:44:28 not ever 01:44:34 unless someone pays me to add it :P 01:44:40 ;)) 01:44:45 lol 01:44:54 its not the principal, its the MOONEY!!! 01:44:57 lol 01:45:06 i stole that off somone i knnow :P 01:45:13 the blob clutter is wrotten by bad coders ;)) 01:45:37 * I440r points /you in the direction of 2904865924765978236459786294564293 billion bad coders 01:46:12 good projects are made better way - universal in one filezz, machine-dependendat - in specific dirs 01:46:34 tell linus that 01:46:53 there isnt a linux kernel source 01:46:57 theres a linux kernel sources 01:47:16 ??? 01:47:28 its like the old joke the MD of pepsi told about coke not being able to say "coke is it" they have to say "coke ARE it" 01:47:48 i seen it in DJGPP compiler and Allegro GFX lib, in free ZIP 01:48:09 so, what the way linux kernel is written ? 01:48:24 i looked slightly but don't recall 01:48:50 i avoid looking in those areas 01:48:58 its badly formatted and totally uncommented 01:49:03 and thus CLOSED source 01:49:25 LOCKED src ;)) beyond seven seals ;)) 01:49:35 :) 01:49:54 iz ze phrase correct grammarly ? 01:50:16 eek! 01:50:20 look at the time lol 01:50:24 i need to go zzz 01:50:32 i didnt realise its like almost 5 am lol 01:50:38 g'nite ;)) 01:50:47 i dunno it looks like it could be right :) 01:50:59 g'morning, LOL ;)) 01:51:00 only the "elete" get to read those sources and understand them 01:51:13 "it was hard to write, therefore it should be hard to read" 01:51:23 which is an attitude im diametrically opposed to 01:51:42 easy to code, easy to grok ? 01:53:40 yes but "difficult to code == MUST be explained in full" 01:53:51 both in the documentation AND in the comments 01:54:18 dont give up on isforth, i do still consider her to be in beta 01:54:28 ;)) 01:54:36 anyway zzzzz (snort!) 01:54:49 bye ! 02:08:13 hey 02:08:21 hi 02:08:21 * mur was thinking forth yesternight 02:08:28 ;)) 02:08:37 and that you thought out ? 02:08:39 about having library 02:08:49 so there were humane commands 02:08:58 like library "mylib" . 02:09:12 . would execute, and 2 and parameter and one is opcode 02:09:21 library of what ? 02:09:23 2nd 1st 02:09:25 umm.. 02:09:36 well then there was more structuralised system 02:09:46 linguistic to program 02:10:06 like select canvas of window2 . 02:11:18 hmmmm.... 02:11:27 way far from my interests 02:13:12 more human readable sourcecode 03:11:50 --- join: qFox (C00K13S@cp12172-a.roose1.nb.home.nl) joined #forth 03:22:05 --- quit: Serg (Read error: 60 (Operation timed out)) 03:24:54 --- join: Serg (~knoppix@193.201.231.126) joined #forth 03:30:44 --- quit: Serg ("Leaving") 03:57:17 --- quit: qFox ("this is mirc's last attempt of communication...") 05:37:50 --- join: tathi (~josh@pcp02123722pcs.milfrd01.pa.comcast.net) joined #forth 05:37:50 --- quit: crc (Read error: 104 (Connection reset by peer)) 06:17:13 --- quit: tathi ("leaving") 07:27:44 --- join: qFox (C00K13S@cp12172-a.roose1.nb.home.nl) joined #forth 07:47:14 Hi 07:51:21 HI TEH ROBRET!!!1 07:51:48 HAI 07:51:56 Someone's in a forthy mood todat. 07:51:58 today 07:52:06 Forthy!!! 07:52:17 What did you take? :) 07:53:10 https://sourceforge.net/projects/forthy 07:54:59 Sexy 07:56:25 muppets and robbets 07:57:10 mur: Do you use the letter 'å' in Finnish? 07:58:06 no 07:58:19 Bah, heathensö 07:58:23 er, -ö :) 08:00:20 I'm thinking of adding prefix and postfix delimiter parsing to Forthy. 08:21:23 heathen's island 08:28:39 madgarden> what happens if you type a space ot the end of a line in your forth? 08:30:46 Nothing. 08:31:02 what would be the difference? 08:31:19 Difference, of what? Not sure what you're asking. 08:31:24 [17:00:12] I'm thinking of adding prefix and postfix delimiter parsing to Forthy. 08:32:09 --- join: fridge (~hovil@CommSecureAustPtyLtd.sb1.optus.net.au) joined #forth 08:32:19 Oh. I mean, you'd be able to register delimiter parsing steps, say making " a postfix delimiter. So then, you could do stuff like this: 08:32:19 print"No space at the start" 08:32:45 oh, then i didnt understand you right :) 08:32:49 :) 08:32:59 Just a way to have more control over the syntax. 08:33:01 but um 08:33:14 doesnt the delimiter prefix word have to take care of that anyhow? 08:33:26 thats how i imagined implementing it in my forth 08:33:46 like, ( would just put the input locator to the next char after ) 08:33:49 The delimiter postfix word would be print" 08:34:13 " is part of the word, but also behaves like whitespaces. 08:34:28 hm yes, but i still dont see the use of it really 08:34:28 So parsing continues directly after the " 08:34:36 I just showed you an example. 08:34:54 Otherwise, you'd be doing this: 08:34:54 print" Space at the start" 08:35:00 brb, must get cleaned up 08:35:17 hmmm, do you mean a seperate word that just scans for the next " and puts the input buffer pointer ahead, so you wont have to do it in a parsing word every time? 08:35:29 hmm 08:35:50 ok i think i get it :) 08:37:09 but then, C" hi" would "kind of" become C hi" ,because the first " is stripped leaving the executing word C (which would do the same as C" in this case) 08:37:47 --- join: kc5tja (~kc5tja@66-74-218-202.san.rr.com) joined #forth 08:37:48 it could work i guess 08:37:54 --- mode: ChanServ set +o kc5tja 08:41:42 qFox: Hey. Not sure if you read the channel logs or not, but the Kestrel has changed yet again. Due to various reasons, I've decided to eschew the 65816 processor, and place a MISC processor of my own design in. 08:42:13 kc5tja> nah i dont read the logs :) 08:42:34 but ok... that tells me very litte tbh :) 08:42:42 I figure, since I'm spending all this money (or, will be, more accurately) on custom logic investments, I might as well go all the way and custom design the CPU to the precise bus specifications I need too. 08:42:56 :) 08:42:59 Well, the P24 is a MISC processor, right? 08:43:11 Expect the Kestrel's CPU to be more similar to the P24 than to the 6502. 08:43:27 if you say so. those details go past me. its information i dont really need 08:43:34 ah 08:43:42 that i can use :p the p24 is hell easy 08:44:16 I'm rather shocked that you didn't know the P24 is classified as a MISC-architecture CPU. I thought it would have been very well documented as such. 08:44:18 compared to the x86, trying to port my little forth program but geez, i forgot the significant differences between p24 asm and x86 asm :p 08:44:46 well, i dont even know what MISC-architecture means. i know its cpu related, but thats about it 08:44:57 remember, i'm not the hardware guy :) 08:44:58 Minimal Instruction Set Computer. 08:45:02 oh 08:45:11 ok i'll be shaming myself in that corner now. 08:45:13 versus RISC -- Reduced Instruction Set Computer. 08:45:21 versus CISC -- Complex Instruction Set Computer. 08:45:29 P24 is MISC, PowerPC is RISC, and 80x86 is CISC. :) 08:45:32 x86 - dont even try? :) 08:45:55 well ok, the 6502 was cisc? 08:46:09 Actually, with the sole exception of the limited set of registers, x86 assembly is vastly easier than VAX-11 assembly. 08:46:27 never even messed with that, but i'll take your word for it :) 08:46:42 how many registers and stacks will your cpu have? any specs in mind? 08:46:43 6502 was technically CISC, but it was built like a RISC machine. It had very few instructions, but lots of addressing modes. It also had RISC-like performance. 08:46:51 and how deep do you think the stacks will be? 08:47:02 Two registers: A and B, used for addressing memory. 08:47:24 There will be two stacks, each 33-bits wide: one for data, one for return. Both are 16 elements deep. 08:47:43 cant possibly make the return stack double of that? ;) 08:48:00 i noticed i use alot of return stack depth in my program, and thats just parsing and stuff... 08:48:23 I can make it double that, but it uses up chip resources to do so. 08:48:39 i'm sure i can do with less (And i dont believe i cross the 16 stack depth) but there's also the user that could use the return stack etc... 08:48:40 (and I haven't even selected a chip yet, so I'm kind of designing for minimum cost right now) 08:48:45 ah true 08:48:50 --- join: Serg (~knoppix@193.201.231.126) joined #forth 08:49:18 The thing is, if you need the return stack depth, you can also perhaps consider manually "spilling" the return stack to memory. 08:49:23 well for a real misc, you can do with a subset of the p24 instructions 08:49:50 yes, thats a speed vs .... stackdepth matter 08:49:53 Most RISCs, for example, don't even *have* a stack in hardware, and implement what basically turns out to be a single-cell return "stack" for subroutine handling. So I know it's possible. 08:50:18 storing/retrieving just takes a couple more instructions (and, i imagine, would be slower then a hardware stack) 08:50:30 qFox: Well, the instruction count I'm looking at right now is roughly in the 40 to 50-ish range, which is too much. 08:50:38 I'm simplifying things still. 08:50:38 yes, boombox told me the x86 emulates the stack with the memmory too 08:51:02 Well, it's a true stack -- it just resides outside of the CPU. 08:51:24 (and therefore, is easy to access like an array, which leads to all sorts of interesting problems and solutions) 08:51:27 i'd say the p24 set is a good guideline. if you have instructions to spare there are a few fast shortcuts i can reccommend :p 08:51:46 recommend 08:51:52 Go ahead and e-mail me your recommendations at kc5tja at arrl dot net. 08:52:06 Here is what I have so far: 08:52:24 Program flow: JMP, JZ, JC, CALL, SYS, RET, NOP 08:52:37 Arithmetic: +, -, *+, /-, NEG 08:52:47 qFox, re but then, C" hi" would "kind of" become C hi" ,because the first " is stripped leaving the executing word C (which would do the same as C" in this case) 08:52:59 The " isn't stripped. 08:53:14 It's just treated like whitespace. 08:53:18 Logical: AND, OR, XOR, COM, 1<<, 2<<, 4<<, 8<<, 16<<, 1>>, 2>>, 4>>, 8>>, 16>> 08:53:21 madgarden> ah ok 08:53:21 So... C"hi" 08:53:28 But, the word in the dict is still C" 08:53:47 Load/Store: @A, @A+, @B, @B+, !A, !A+, A!, B!, A@, B@, R@, >R, R>, SPR!, SPR@ 08:53:57 Stack: DUP, OVER, SWAP, DROP, NIP, ROT 08:54:14 Lots of instructions, most of them put there for convenience reasons. 08:54:23 kc5tja> jc = jump if carry set? sys i dont know. those <<>> can be done away with by just adding shr/shl imo. spr!/@ i dont know. nip i should know but dont :\ 08:54:52 and where is your literal instruction? 08:54:55 qFox: Well, if you're going to be doing graphical stuff, you want fast shifts and rotates. 2* 2* 2* 2* 2* 2* 2* 2* is 8 cycles, while 8<< is only 1. 08:55:03 jc is jump on carry set, yes. 08:55:25 SPR@/! are fetches and stores to CPU-specific "special purpose registers," which control various aspects of the CPU without additional instructions. 08:56:08 For example, I was thinking of making A and B two SPRs, but then loading and storing to them would take two cycles, not one, so I re-introduced A!, A@, B!, and B@ as separate instructions, since they're so heavily used. 08:56:23 NIP is equivalent to SWAP DROP 08:56:29 ah ok 08:56:37 it drops the 2nd top of stack, not the 1st top of stack. 08:56:51 A! A@ is ST LD, how do you put something from T to A/B ? 08:57:11 A! and A@ will store T in A, or fetch A into T, respectively. 08:57:17 oh 08:57:18 You're thinking of !A and @A 08:57:27 i guess so, my mistake :) 08:57:27 Store-with-A and fetch-with-A. 08:57:41 Yeah, it's confusing, but it's also intended to be hidden by the system's Forth compiler too. 08:57:45 :) 08:57:47 true 08:58:02 you could, to save instructions.... only allow direct memmory storing/fetching via reg A 08:58:12 opencores has come a long way from when I last checked 08:58:16 Also, it is a word-addressed machine, like the P21/P24. Consequently, it has 4.2GB, but each "byte" is 32-bits wide! 08:58:24 understood 08:58:31 makes it easier though 08:58:32 So, all total, it addresses 64GB of 8-bit equivalent memory. 08:58:51 however, you "could" add C@ C! equilavents (uh or something :) 08:58:58 equivalent 08:59:01 * qFox cheats 08:59:22 Well, that's one reason why I wanted all those shift operators; to expidite sub-field accesses. 08:59:31 come again? 08:59:38 But then, after I came up with them, I recalled the PowerPC's most God-like instruction: rlwini. 08:59:58 It's a mouthful, but it does a rotation, a masking, then if you want, a shifting. :) 09:00:09 In short, it's a bit-field extraction instruction. 09:00:15 well, you have 32bit cells. what size instruction were you thinking about? 09:00:31 The instructions are 6-bits wide, packed 5 across in a single cell. 09:00:47 ok 09:00:56 Not sure what to do with the remaining 2 unused bits, but I'm thinking of making them the least significant bits of a 7th instruction. 09:01:09 err, 6th instruction rather. 09:01:34 imo, you can do away with the jnc, i havent come up with any use for it just yet 09:01:36 Capable of holding NOP, JMP (what you'd normally use), RET, or SYS. 09:01:38 --- join: tathi (~josh@pcp02123722pcs.milfrd01.pa.comcast.net) joined #forth 09:01:46 I use it constantly. 09:01:49 ohyes, whats sys? 09:01:56 Oh, sorry. 09:02:20 SYS is a software interrupt -- it is basically a compact short-hand for invoking a system call. It's literally equivalent to CALL $00000010. 09:02:29 ok 09:02:43 It's faster (one cycle instead of two), and more compact (6 bits instead of 44). 09:02:55 In all other respects, it behaves exactly like CALL. 09:03:31 for the instructions to add... add ZERO, to put a 0 on the stack. or a ONE if you prefer dupdupxor for 0. 0 and -1 can be done in 4 and 5 instructions, but 1 takes up lit and the next XT 09:04:45 and for protection reasons i kind of resented using ldp (!A+) for this, as you might be reading from non-existent or illegal space... 09:04:51 so to speak 09:05:08 Well, now you're treading into SPR territory. :) 09:05:13 oh 09:05:19 I've got plans to release a future version of the processor with an integrated MMU. 09:05:19 ok then :) 09:05:40 Working on the Kestrel again? 09:05:53 I want it powerful enough to run something like Linux. Not saying that I will port Linux (I'll leave that to someone else to try), but that's my goal. 09:06:11 tathi: Yes. Gone is the 65816 processor. A stack CPU will now be at its heart. 09:06:32 awesome. 09:06:39 i've been busy on my math all day. derivatives make this look so easy suddenly :p 09:06:59 Wait until you get into integration; derivatives will be trivial in comparison. :) 09:07:16 "the PowerPC's most God-like instruction" :) Yay rlwinm! 09:07:19 well dont know the dutch term for that, but i'm sure i'll come accross it 09:07:34 only halfway now 09:07:39 qFox: inverse operation of the derivative. 09:07:45 oh... goody :\ 09:07:52 integration is the process of finding the anti-derivative. 09:08:13 tathi: :) 09:08:26 I should read up on rlwinm again, to see what ideas I can leech from it. 09:08:37 And how I might be able to implement it in the MISC core. 09:09:03 yeah, I'm not sure how that would work, seeing as it has five operands... 09:09:13 --- quit: fridge (Remote closed the connection) 09:09:27 I'd probably make each "sub-step" of the rlwinm dataflow a separate MISC instruction. 09:09:37 i was thinking btw. in math, when one finds a certain algoritm to solve/prove something, its free to be used by anyone. no charges, no copyright, nothing. in programming when someone thinks of a certain algoritm, he or she holds some kind of copyright for it.... however imo you can compare the two as being sort of the same 09:09:52 That would keep the stack usage low, but at the cost of run-time performance (OTOH, it'd be easier to drive to higher clock speeds) 09:09:56 except mathimatical algoritms arent appealing to the public, so to speak 09:10:10 --- join: fridge (~hovil@CommSecureAustPtyLtd.sb1.optus.net.au) joined #forth 09:10:13 but its kind of odd 09:11:07 anyways, i'll try to setup a 6bit instruction set with 2 regs. 09:11:08 qFox: This is the whole crux of the patent problem with respect to software. It's a loophole in the patent system that is being exploited, and lots of people are making money off of it. Software patents are *EVIL* and have done *FAR* more harm to restrict industry growth than anything Microsoft could have done to date. 09:11:09 yeah, rlwinm seems kind of counter to the RISC concept, IMO 09:11:40 yep, i had the same idea 09:11:42 tathi: But at the same time, it is the epitome of RISC, too -- all it does is exploit the already existing data path through the PPC's ALU. 09:12:50 kc5tja: Oh. OK, never thought of it that way. Makes a lot of sense though. 09:15:26 :) 09:15:48 It seems to be simple enough, from what I'm reading. 09:15:53 http://publibn.boulder.ibm.com/doc_link/en_US/a_doc_lib/aixassem/alangref/rlwinm.htm 09:16:10 I would definitely break this up into 3 separate instructions though. 09:16:21 --- quit: Serg ("Leaving") 09:16:22 kc5tja> looking from a p24 point of view, will you allow manipulation (read/change) of the I and P registers? 09:16:28 One for rotation, one for bitmask generation, and the final AND. 09:16:41 the current instruction word in the cpu, and the adr of the next instruction word 09:16:42 qFox: What are the I and P registers? 09:16:58 ^ 09:16:59 instruction latch and program counter? 09:17:02 yes 09:17:06 Well, P is changed via JMP, CALL, RET, etc. No point in making that an explicit operation. 09:17:22 The I register is off-limits to the programmer though, since it's value is constantly changing on each clock cycle. 09:17:37 k, no reading either? 09:17:45 Why would you want to? 09:17:53 dont know. just curious 09:17:54 :) 09:18:01 perhaps for debugging purposes 09:18:20 The state of the I register is deterministic to the point where you can literally push a literal constant on the stack to represent the state of the I register at the time the LIT is executed. :) 09:19:23 I might, in the future, introduce a "return from interrupt" instruction which reloads the I register with a value on the return stack (this is required to handle, for example, page faults or other access violations). 09:19:54 and, will it have T S and R registers like the p24 has? these are readonly (in fact, i'm not sure if those werent just for the theory...) 09:20:06 T is top of datastack, S is NOS, R is top of return stack 09:20:20 Those "registers" are not programmer visible, even in the P24. 09:20:31 ye was just realizing that :p 09:20:34 They are used only to explain what's going on inside the chip. 09:21:05 However, the architecture of a MISC will always have those "registers," and I will also be using those theoretical registers to explain the operation of the instructions. 09:24:19 tathi: Actually, I don't need a separate instruction to generate the bitmask. That can be computed using existing means. I didn't realize that rlwinm used fixed constants to generate the bitmask with. 09:24:26 So really, the only thing I need is the rotation. 09:25:57 qFox: In light of the conversation between me and Tathi, I'm thinking of changing the shift instructions around a bit. Basically have 2* and 2/ for single-bit shifts, then have a general purpose << and >> for shifts, and <- and -> for rotations. 09:26:26 so shifting something by 5 bits would be like: 5 nop nop << (or something like it). 09:26:44 The nop's would give the shifter enough time for the data to propegate through the shifter unit. 09:26:56 hmmm 09:27:16 perhaps, instead of a whole range of instructions for that 09:27:29 you can do << >>, and the next instruction would be the argument 09:27:35 No. 09:27:48 Zero-operand is a most holy goal. 09:27:49 or something..? :) 09:27:50 Trust me. 09:27:53 ok 09:28:00 It *really* simplifies the CPU design to have *everything* on the data stack. 09:28:16 same thing... 09:28:20 well, same idea 09:28:33 or was that what you meant 09:28:43 The only instruction that takes its operand from the I register are JMP, JC, JZ, and CALL. Those are the only four instructions to do so. 09:29:15 and literal? 09:29:17 oh 09:29:21 nm thats not I 09:29:40 Nope. It takes the literal from memory at P, then increments P. 09:33:36 Yes, I like this idea. A lot. 09:33:38 Consider it done. 09:33:39 :) 09:34:12 << >> taking argument from the stack? 09:34:20 They take two arguments. 09:34:26 << ( n sh -- n< >> ( n sh -- n>>sh ) 09:34:31 oh right 09:34:32 yes 09:34:58 Same thing with <- and -> (rotate instructions, not shift). 09:35:18 ok, and um, why *+ and /- ? 09:35:33 isnt * / faster? 09:35:56 or am i reading it wrong 09:36:00 * and / take hardware resources that may make it impossible to program the processor on cheap FPGAs. 09:36:23 Otherwise, you'd be correct, having a real * and / instruction would be much faster. 09:36:48 But, still, *+ and /- would be rather fast too. Certainly MUCH faster than implementing the shift-and-add or shift-and-subtract algorithms by software alone. 09:37:13 hmmm you mean like, S*T+x, where x is from an external device? 09:37:41 No. I mean the multiply step instruction, as found in the P21 and P24. 09:38:44 oh, so *+ is not a complete multiplication 09:39:02 Nope. Just a single bit. 09:39:24 right 09:40:06 i've never grasped the whole external hardware thing from the p24 (since i never had to implement it ;) 09:41:04 It's really not that hard. Each hardware device has a limited amount of memory -- called registers -- that not only store values, but *do* things when you write to them. 09:41:31 That is, the very act of writing data to them causes the hardware to actually undertake some action. In most cases, that action depends on the value being written. 09:41:39 Sometimes, actions can also occur when reading from a register too. 09:41:47 (usually things like clearing interrupt pending bits and the like) 09:47:51 but in the p24, you could only shift one bit per instruction to, and read one bit from it 09:48:01 with shr and div, i think 09:48:49 I don't think we were talking about the same thing. 09:48:53 Please start over. 09:50:35 for some reason, the whole http://www.eforth.com.tw/academy/sutra/chapter9.htm thing is gone 09:50:44 i saved it somewhere on my laptop though, hold on :) 09:52:46 or did i... 09:55:22 Add the S register on the data stack to the T register. If the addition produces a carry place the sum in T, otherwise leave T unchanged. The T-A register pair is now shifted to the left by one bit. Carry is shifted into A(0). 09:55:27 (for div) 09:55:30 Hmm, I now have 43 instructions listed. 09:59:14 Down from 47 10:00:38 oh right i was composing a list 10:02:42 is it possible to add a * or / in just one instruction? 10:02:44 SYS is gone. 10:02:51 i mean, wouldnt that increase speed alot? 10:03:03 in general 10:03:11 Not without MASSIVE hardware resources. 10:03:50 hm ok, pity 10:04:05 And the faster you want it, the more hardware it'll take. 10:04:25 --- join: SDO (~SDO@co-trinidad1a-156.clspco.adelphia.net) joined #forth 10:04:32 For example, a 32 by 32 multiplier will require 4096 AND gates at a *minimum* to implement, not counting all the intervening adders as well. 10:04:51 re SDO 10:04:56 hm, right 10:05:01 hello kc5tja 10:05:07 SDO: The Kestrel will no longer use the 65816 for its CPU. 10:05:13 In its place will exist a MISC core. 10:05:39 Well, Chuck won't think it'll be MISC, but compared to RISC, it's definitely a vast improvement. :D 10:05:49 ah, well hope it will be cool anyway. 10:05:55 It will be. 10:06:30 Two things: it eliminates a lot of nonsensical hardware requirements that the 65816 required for proper operation. Second, it'll run at 25.175MHz, and third, it'll actually get 25.175MIPS peak performance. 10:06:48 e.g., a simpler CPU results in a 4x performance improvement, AND it's a true 32-bit CPU, not 8/16-bit. 10:07:11 It'll address 64GB of RAM (well, the CPU thinks it's 4.2GB, but remember it has 32-bit wide bytes!). 10:10:39 --- join: Serg (~knoppix@193.201.231.126) joined #forth 10:11:51 hm wait, how do you get to 64? 10:11:56 --- quit: Serg (Client Quit) 10:12:08 2^32 is 4gig, which already involves using ret 10:12:28 4.2 billion memory cells, each of which is 32-bits (e.g., 4 octets) wide. 10:12:37 oh ok 10:12:53 and i was just wondering 10:13:06 say you jump to a 32bit adr using ret 10:13:23 if, at that code, you use jump or jz, where would you end up? 10:13:38 the 28bit addr in that segment? or the absolute addr? 10:14:07 Somewhere int he 26-bit range in that segment. 10:14:22 The way my control flow words work is a bit mind-bending, but I can assure you there is a reason to my madness. 10:14:22 uhm, yes i meant 26 :) 10:14:47 i'm sure there is, but i was just thinking that i have no idea how the p24 handles this 10:14:49 When JUMP executes, it'll occupy, guaranteed, slot 0 (bits 0-5). 10:14:55 yes 10:15:05 Bits 6 through 31, then, contain an effective address for JUMP. 10:15:15 yes 10:15:18 Problem is, as instructions are executed, the I register is shifted to the right, with zeros coming in on the left. 10:15:58 So the address field is *NOT* the physical address it jumps to; rather, it's a bit-mask that is XORed with the P register to determine the target address. 10:16:22 yes, so relative jumps in the segment 10:16:28 This lets the JUMP instruction execute the same way, with the same hardware resources, all the time, every time, regardless of what slot it appears in. 10:16:47