00:00:00 --- log: started forth/03.12.02 00:02:56 --- quit: chandler (calvino.freenode.net irc.freenode.net) 00:07:46 --- join: chandler (~darmok@64-145-60-36.client.dsl.net) joined #forth 00:10:59 --- join: njd (~junk@njd.paradise.net.nz) joined #forth 00:11:28 --- quit: Herkamire (Read error: 60 (Operation timed out)) 00:20:00 --- quit: Robert (Read error: 113 (No route to host)) 00:24:18 --- join: Robert (~snofs@c-2b5a71d5.17-1-64736c10.cust.bredbandsbolaget.se) joined #forth 03:39:37 --- join: _gps_ (~gps@166.70.196.201) joined #forth 05:03:55 --- quit: haroldo (Read error: 104 (Connection reset by peer)) 05:09:08 --- join: haroldo (~haroldo@r200-40-216-117.adsl.anteldata.net.uy) joined #forth 07:05:14 --- join: yasam (~sam@210-55-32-49.dialup.xtra.co.nz) joined #forth 07:11:24 --- join: I440r (~mark4@saturn.vcsd.com) joined #forth 08:01:02 --- join: schihei (~schihei@pD9E5C5D2.dip.t-dialin.net) joined #forth 08:11:43 --- join: Herkamire (~jason@h000094d30ba2.ne.client2.attbi.com) joined #forth 10:08:56 --- join: Robert_ (~snofs@c-2b5a71d5.17-1-64736c10.cust.bredbandsbolaget.se) joined #forth 10:18:51 --- join: kc5tja (~kc5tja@66-91-231-74.san.rr.com) joined #forth 10:18:51 --- mode: ChanServ set +o kc5tja 10:21:54 kc5tja: I'm ready to give arch a spin. where can I access qm? 10:23:01 --- quit: Robert_ (Read error: 104 (Connection reset by peer)) 10:23:03 --- join: Robert__ (~snofs@c-2b5a71d5.17-1-64736c10.cust.bredbandsbolaget.se) joined #forth 10:23:25 The archive is at kc5tja@arrl.net--qm-2003: http://www.falvotech.com/{archives}/qm-2003 10:24:42 Note that I don't have anything compiling yet, except for the documentation (you need to have nuweb and some kind of LaTeX installed on your box to do it though). 10:24:47 But it'll generate source code. 10:25:06 That's a start at least. :) 10:25:45 fun 10:25:59 I installed tetex and tla this morning 10:26:12 I'm downloading nuweb (no ebuild for it :( ) 10:26:30 --- quit: Robert (Read error: 110 (Connection timed out)) 10:26:55 hmmm. actually tetex is just starting to install 10:27:39 Yeah. tetex is rather large. 10:28:53 what !@#$ jackass made the nuweb tar? 10:29:18 it does not contain a directory, and it's not compressed 10:29:23 glad I checked 10:30:08 --- quit: yasam (Read error: 113 (No route to host)) 10:30:31 Hmm, I should have warned. Sorry. 10:32:07 --- join: Robert (~snofs@c-2b5a71d5.17-1-64736c10.cust.bredbandsbolaget.se) joined #forth 10:33:59 What version of tla are you using? 10:34:41 tla lord@emf.net--2003b/dists--release-tla--1.1--patch-7(configs/emf.net/devo.tla.release) from regexps.com 10:36:52 and I was already annoyed about having to go through all the extra mirrored download BS at sf.net 10:37:03 Hmm...I was expecting you to get 1.1p9. :) I have p8. 10:37:21 ?? I got mine from Savannah. 10:39:50 I just installed with gentoo. maybe I haven't updated my portage tree lately. I'll check for a newer install script 10:40:14 I'm confused. 10:40:20 I am pretty sure tla isn't on SourceForge. 10:40:38 I downloaded nuweb from sourceforge 10:40:43 But whatever. 1.1p7 *should* work; if not, I'd consider grabbing at least p8, if not p9. 10:40:54 Oh. nuweb. I thought you were talking about tla. :) 10:49:57 --- quit: Robert__ (Read error: 110 (Connection timed out)) 11:21:19 --- quit: I440r ("Leaving") 12:49:24 --- join: Robert_ (~snofs@c-2b5a71d5.17-1-64736c10.cust.bredbandsbolaget.se) joined #forth 12:50:48 --- quit: Robert (Read error: 104 (Connection reset by peer)) 12:57:54 --- quit: warp0x00 ("#") 13:14:00 --- quit: Robert_ ("brb") 13:31:53 --- join: Robert (~snofs@c-2b5a71d5.17-1-64736c10.cust.bredbandsbolaget.se) joined #forth 13:56:53 --- join: ez4 (~ez4@pcp01518726pcs.reding01.pa.comcast.net) joined #forth 15:27:42 --- quit: schihei (Client Quit) 16:11:26 --- log: started forth/03.12.02 16:11:26 --- join: clog (~nef@bespin.org) joined #forth 16:11:26 --- topic: 'where people get together to talk about CVT, stirling engines, tesla turbines, data structure and algorithm design, and occasionally Forth' 16:11:26 --- topic: set by kc5tja on [Wed Oct 15 21:47:35 2003] 16:11:26 --- names: list (clog ez4 Robert @kc5tja Herkamire haroldo _gps_ njd chandler arke ianp mmanning @ChanServ onetom madgarden mur skylan oooo_ MysticOne TreyB) 16:12:22 What of it? 16:12:26 kc5tja: They're going to have just once license class here soon. 16:12:35 well, im trying to figure it out 16:12:38 input: I, C 16:12:43 output: R1, R2 16:13:10 kc5tja: So everyone will be able to use all bands with 1kW output power (except the LW and warc bands). 16:13:30 Robert: Sorry to hear that. 16:14:05 kc5tja: I'm not, because I want to do that (of course with a bit more QRP levels). :) 16:14:17 While I don't necessarily agree with requiring morse code proficiency, I think it's vitally important to maintain different classes of licensees (at least two!) to provide incentives to learn the technological and legal aspects of the hobby. 16:14:50 arke: There is not much to figure out. 16:14:57 Well, the education was the same before anyway. 16:15:09 But you had to know morse code to use the shortwave bands. 16:15:12 kc5tja: I don't get it :) 16:15:33 So the only difference is that people who don't know morse code can use SSB on the shortwave bands. 16:15:48 arke: You have two J/K flip-flops. You tie the J and K inputs high to set them into toggle mode. The input clock works with the least significant bit. The Q output of the LSB goes to the next bit's clock, etc. 16:17:11 er.. 16:17:13 uum 16:17:16 hold on 16:18:53 Robert: Here, we have three license classes. Technician tests concentrate more or less on the legal aspects of the hobby. General concentrates more or less on RF propegation and some more advanced electronics background. Extra class is more heavily electronics influenced. 16:19:07 So as you go up in license class, the more technical your tests become. 16:19:22 do you have dia? 16:19:26 And if you pass, you get wider operating privileges (e.g., more frequencies at your disposal, etc) 16:19:50 arke: no 16:20:02 Nor do I intend on getting it. dia sucks ass. 16:20:03 kc5tja: ugh. any other flowchart program or such? 16:20:10 heh 16:20:16 Nope. I have xfig though 16:20:44 ugh. 16:20:51 just get something please? :) 16:20:55 xfig. 16:21:07 You need a picture? I'll put it out as a PNG file. 16:21:11 oh, i have that :) 16:21:15 i have xfig 16:21:16 kc5tja: Oh, OK. Here we have to learn about electronics _and_ legal aspects to get the license. That way even 13 year old VHF users get to learn about how radio receivers work ;) 16:21:42 Robert: Well, that's basically the case for tech licenses here too. 16:21:55 What I'm saying is, as you approach extra class, you have to know more about how to build them. 16:22:12 Ah, okay. And you need that for SSB on the HF bands? 16:23:36 --- part: madgarden left #forth 16:23:44 ugh 16:23:52 xfig doesnt have jk flipflops 16:24:57 --- join: Sonarman (~matt@adsl-64-169-94-105.dsl.snfc21.pacbell.net) joined #forth 16:26:54 Robert: Would you rather we let the drunken retards on our CB bands influence international conversations? 16:27:04 arke: Dude, I'm drawing them by hand. They're not hard. :) 16:27:42 i know how they look like, i just hoped xfig would have them in its lib 16:32:49 i dont like xfig 16:34:12 kc5tja: They can do it on the CW bands already, can't they? 16:34:29 Robert: illegally. 16:34:44 Robert: It's much harder to talk trash in CW too. 16:34:54 arke: My PNG converter isn't working for some retarded reason. 16:34:57 So I have it in PDF format. 16:35:01 Unless you want the actual .xfig file. 16:35:05 kc5tja: Wait, weren't they allowd to use CW but not SSB? 16:35:14 Robert: Define `they'. 16:36:01 The drunken retards you were talking about.. I thought you were talking about people with your license class. 16:36:11 Who aren't allowed to use SSB. 16:36:16 Robert: Huh??? CB is wholesale unlicensed here. 16:36:55 Robert: It's a free-for-all mosh-pit of libel, slander, drunkenness, unintelligable dolts who think voice-boxes are the coolest things since sliced bread. 16:37:11 Er, sorry. Misunderstood you :) 16:37:25 kc5tja: sure, ill take the xfig file 16:37:30 Then I get what you mean.. anyway, those aren't allowed to use the amateur bands here either. 16:37:32 arke: E-mail address? 16:37:37 DCC SEND 16:37:41 arke: No can do. 16:37:44 arke: Firewall. 16:37:49 ugh 16:37:55 chris at waltoncity dot com 16:38:28 * MysticOne smacks kc5tja with a cow 16:39:13 Moo. 16:39:55 Moof! 16:41:16 fwong! 16:43:43 theres this kid at my school who's called Richard Wang 16:44:45 Nothing tops the twins that arrived at our highschool. 16:44:46 hahaha 16:44:48 Dick Wang 16:45:05 The brothers were named Ding and Dung, respectively. 16:45:10 kc5tja: haha 16:46:03 arke: The file has been sent. 16:46:06 Not sure if you got it yet or not. 16:48:22 i got it 16:48:24 how does it work? 16:48:30 and does it use only one clock cycle? 16:48:38 what is it? 16:50:23 u da man! :) 16:53:11 * MysticOne wants to know what the program does! 16:55:00 its a 2-bit counter 16:55:27 kc5tja: whats teh dots? 16:55:47 arke: Each clock's rising edge causes the counter to increment by one. 16:56:05 arke: When the counter is reset (somehow, I deliberately left that detail out), all Q bits are 0. 16:56:08 * MysticOne doesn't understand 16:56:19 Thus, the J/K inputs of bit 1 are low. Hence, any clock on that bit doesn't affect it at all. 16:56:28 MysticOne: Electrical engineering stuff. 16:56:33 oh 16:56:43 The ellipses means "and so in," as it does in English text . . . 16:57:20 When the first clock pulse comes in, bit 0 toggles its Q output to 1 (because it's the only flipflop that has its JK inputs tied high explicitly). 16:57:27 So now the counter reads ...001. 16:57:53 But look at what happens: now bit 1's JK inputs are high, just like bit 0's. So the next pulse that arrives, both bits will toggle: ...010. 16:58:00 00 -> 01 -> 10 -> 11 -> 00 -> ... ? 16:58:17 Ah, but now bit 1's inputs are low again, so the next pulse only affects bit 0 --> ...011. 16:58:44 At this point, if we were to support a bit 2, we'd find that bits 0, 1, AND 2's JK inputs are all high, so the next pulse toggles all three bits: ...100. 16:58:49 And so on, for as many bits as you have. 16:59:57 does it wrap-around? 17:00:09 the guy i talked to today took a class on this 17:00:18 and he wanted me to figure it out 17:00:25 but he gave me a few "hints" 17:00:45 the Q's of the JK's go directly to the results 17:01:02 the results can't be accessed outside of the Q of the JK 17:01:15 the only inputs allowed are C and power 17:01:19 and i really dont get it 17:01:39 The Q's are the results of the counter. 17:01:49 But each bit's Q is used as the input to the next bit in the counter. 17:03:00 he said that wasn't possible in a single-cycle counter 17:03:06 which is what im trying to do here :) 17:07:02 He's flat out of his gourde. 17:08:12 --- log: started forth/03.12.02 17:08:12 --- join: clog (~nef@bespin.org) joined #forth 17:08:12 --- topic: 'where people get together to talk about CVT, stirling engines, tesla turbines, data structure and algorithm design, and occasionally Forth' 17:08:12 --- topic: set by kc5tja on [Wed Oct 15 21:47:35 2003] 17:08:12 --- names: list (clog Sonarman ez4 Robert @kc5tja Herkamire haroldo _gps_ njd chandler arke ianp mmanning @ChanServ onetom mur skylan oooo_ MysticOne TreyB) 17:11:04 --- join: haroldo_ (~haroldo@r200-40-167-6.adsl.anteldata.net.uy) joined #forth 17:15:14 MysticOne: Hey, not sure if you saw or not; got qm's first set of unit tests working. :) 17:15:23 w00t! 17:15:25 * kc5tja is totally loving arch right now, too. 17:15:32 :) 17:15:36 And nuweb, and LaTeX for documentation. 17:15:45 nuweb? 17:15:52 17:17 < topher> " design a sequential circuit with two JK flip flops A nd B and two inputs E and x. if e=0, the circuit remains in the 17:15:52 It's a literate programming tool. 17:15:55 same state regardless of the value of x. when e = 1 and x = 1, the circuit goes through the state transitions from 00 to 17:15:59 01 to 10 to 11 and back to 00 and repeat. when e = 1 and x = 0, the circuit goes through the state transitions 00 to 11 to 17:16:02 10 to 01 and back to 00 and repeat 17:16:04 question from his textbook 17:16:43 arke: OK, first of all, that's a totally different problem from what you described to me. :) 17:16:51 er 17:16:59 it is!? 17:17:06 Yes. 17:17:18 You made no mention, for example, of a direction control bit ('x' in this example). 17:17:21 well, i _still_ can't figure it out. 17:17:40 oh, he said when he told me that i didnt have to worry about that 17:17:52 17:18 < topher> arke: so, slightly different from what i told you, but both are possible. do the one from the book if you think the 17:17:56 simpler one is impossible 17:18:24 Is E the clock input? 17:18:29 Or is it just a `clock enable' input? 17:18:34 The question is ambiguous. 17:18:52 clock enable 17:18:56 says he 17:19:02 So there are actually three inputs, not two. 17:19:18 well, for the textbook version there is 17:20:05 It's tricky, but doable. :) 17:20:51 well, im not completely sure on JK flipflops 17:21:03 The hint is this: a JK flip-flop will toggle only when both J and K inputs are high. 17:21:06 i do know that they take 3 inputs and 1 output 17:21:15 No. 17:21:19 They produce two outputs. 17:21:24 J = the set flag 17:21:27 K = clear flag 17:21:28 Q and /Q (where /Q is the inverted form of Q) 17:21:30 C = clock 17:21:32 Q = result 17:21:37 oh 17:21:38 ok 17:21:50 well, 11 toggles 17:21:56 01 = 0 17:21:58 10 = 1 17:22:04 00 = 0 17:22:06 iirc 17:22:08 nope. 17:22:12 00 = toggle 17:22:15 yes 17:22:16 00 = (remember the same state I was in last clock) 17:22:21 er? 17:22:28 so, like a save? 17:22:38 More like a 'remember.' 17:22:40 or a NOP? 17:22:44 Yes, a NOP. 17:22:44 .... 17:22:45 eeek 17:22:47 lol 17:22:52 this is confusing me 17:23:00 start from the beginning, please :) 17:23:27 A J/K flip flop is basically a really tiny, super-simple, 1-bit processor with four instructions: 17:23:39 JK Desc 17:23:42 00 NOP 17:23:50 01 Q = 0, /Q = 1 17:23:56 10 Q = 1, /Q = 0 17:24:02 11 Q <-> /Q 17:24:13 neat. 17:25:12 --- quit: haroldo (Read error: 110 (Connection timed out)) 17:25:16 Every clock edge (either positive or negative, depending on the precise flip flop used; I assumed a rising-edge-triggered flip flop, which means it acts when the clock is going low to high). 17:25:18 err 17:25:31 every clock edge, the flip flop examines its inputs and determines what to do with its outputs. 17:26:00 --- join: I440r (~mark4@12-217.lctv-a5.cablelynx.com) joined #forth 17:26:22 The trick to solving this 2-bit counter problem is to draw up truth tables, and derive the circuit from that. 17:26:42 Examine when certain output bits toggle, and derive the NAND-gate logic from that. 17:26:52 (oops, I spoke too much. :) ) 17:27:01 well, bit 0 is very easy 17:27:17 you just set J and K 17:27:21 and it toggles 17:27:25 which is all it does anyway 17:27:28 thats not my problem 17:27:29 Yep, bit 0 always toggles, regardless of what direction the counter is counting. 17:27:33 my problem is bit1 :) 17:28:07 so, my bit0 JK takes EE 17:28:09 Well, the schematic I sent you is already half of the answer. 17:28:19 is that a signle clock? 17:28:41 I need a more precise definition of what you mean by `single clock.' 17:30:54 i mean that it only takes one clock cycle to complete the count 17:31:08 JK's are cool :) 17:33:11 Yes, it takes only a single cycle to count. 17:33:16 Otherwise, it wouldn't be much of a counter. :) 17:33:25 :) 17:34:34 heh 17:34:42 remember that nibble-based CPU i made up? 17:34:56 Vaguely. 17:34:59 i could probably find a proggie that does gates and JKs etc. and actually create it 17:35:02 that would be so cool 17:35:09 * kc5tja nods 17:37:04 how to implement memory? 17:37:23 Definitely NOT with J/K flip flops. :) 17:37:30 JKs are huge and relatively slow. 17:37:39 (lots of gates go into making them work.) 17:38:01 Transistor-type R/S flip-flops are often used to implement static RAM. 17:38:10 how do those work? 17:38:20 SR Desc 17:38:25 00 Remember last state 17:38:35 01 Q = 0, /Q = 1 17:38:41 10 Q = 1, /Q = 0 17:39:10 11 Undefined state -- both Q and /Q try to rise, which causes them to ALSO want to drop to zero. Potential short circuit can cause damage. 17:39:22 . 17:39:24 er 17:39:31 ALMOST like JK 17:39:32 lol 17:39:42 R/S flipflops are the simplest possible flip flops. 17:39:53 how are they used for RAM? 17:39:56 They take only two NAND or NOR gates to implement. 17:40:05 One R/S flip flop stores one bit of RAM. 17:40:39 Normally, each bit has an additional set of AND gates on the input. 17:40:59 When a bit is addressed, those AND gates ensure that only S or R are asserted. 17:41:08 er!? 17:41:09 lol 17:41:12 oooh 17:41:13 i get it 17:41:28 CPU sends 00 to keep it in the state 17:41:36 to turn it on, it uses 10 17:41:40 to turn it off, it uses 01 17:41:42 The reason for R/S flip flops is two fold -- small size of the FF means it's possible to pack more on a chip, and also, less gates means they operate faster. 17:41:46 to query it, it uses Q 17:41:48 right? 17:41:53 More or less, yes. 17:42:09 The address bus on a CPU tells the RAM chip which chunk of flip flops to read from. 17:42:20 so the flip flop will always have the state accesible in Q 17:42:35 Always. 17:43:14 sweet. 17:43:17 thats pretty nice. 17:43:46 do you know of a program that allows the creation and testing of logic circuits? 17:43:57 Not off hand, no. 17:44:17 SPICE is way, way WAY overkill for you, and unless you want to learn a whole new programming language, I don't think you'll want to play with Verilog or VHDL. 17:44:38 Plus absolutely none of the tools above are very user friendly. 17:44:39 :) 17:45:00 :) 17:45:53 hrm, i have klogic 17:46:00 i wonder if thats decent. 17:46:09 Don't know. 17:46:11 Not familiar with it. 17:46:20 heehee 17:46:27 it has RS and JK flipflops :) 17:49:43 OK, the next thing to do for qm, I think, is to define the persistence file format, and the readers and writers that work with them. 17:49:44 :) 17:50:07 And to do that, I am going to be needing support for EA-IFF-85a compatible files. >:) 17:58:23 haha yay 17:58:27 klogic works 17:58:56 --- quit: I440r (Read error: 60 (Operation timed out)) 18:00:00 would S or R be Q? 18:02:31 haha 18:02:36 I've got a clock now 18:02:37 :) 18:04:51 S maps to Q, but it doesn't terribly matter. 18:05:17 It all depends on what you want from your application. 18:06:56 OK 18:17:13 --- part: _gps_ left #forth 18:19:20 --- join: I440r (~mark4@12-217.lctv-a5.cablelynx.com) joined #forth 18:21:29 simple if-then-else? 18:22:27 re I440r 18:22:31 hi 18:23:09 :) 18:23:24 kc5tja: i need something really simple 18:23:31 if(a) then b else c 18:23:58 brb 18:24:01 --- quit: I440r ("Leaving") 18:27:15 arke: Can I have some context please? :) 18:29:31 Ouch -- my eyes are sore. 18:29:40 I hate it when that happens. 18:30:09 heh 18:30:13 i think ive already got it 18:35:38 * kc5tja thinks he's coming down with a cold. :( 18:39:52 whats a D flipflop? 18:51:26 It's an R/S flip flop with an integrated inverter, so that the R and S inputs can never, ever be the same value. 18:51:32 D = "Data" 19:02:12 er 19:02:22 logic table? :) 19:04:41 Ummm....none is needed. 19:04:49 When D = 0, S = 0, and R = 1. 19:04:54 When D = 1, S = 1, and R = 0. 19:04:54 :) 19:04:56 That's it. 19:05:11 It's not possible to have illegal or NOP states with D latches. 19:06:16 hrm 19:09:34 klogic allows you to define your own circuits 19:29:41 --- join: I440r (~mark4@12-217.lctv-a5.cablelynx.com) joined #forth 19:30:14 Ever be so tired that you cannot sleep? 19:30:19 That's basically the state I'm in today. 19:30:23 Gahh.. 19:41:00 --- quit: I440r (Read error: 104 (Connection reset by peer)) 21:26:23 --- quit: ez4 () 21:57:34 --- quit: Sonarman ("leaving") 22:13:27 --- quit: Herkamire ("bedtime") 22:19:53 Well, I'm off to bed. 22:20:01 --- quit: kc5tja ("THX QSO ES 73 DE KC5TJA/6 CL ES QRT AR SK") 22:26:34 --- join: Serg_Penguin (~z@212.34.52.140) joined #forth 22:42:00 --- join: I440r (~mark4@12-217.lctv-a5.cablelynx.com) joined #forth 23:59:59 --- log: ended forth/03.12.02