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17:41:59 <kc5tja> Hello.
17:43:12 <warp0x00> sup
17:44:49 <kc5tja> Just got back from work.
17:45:19 <kc5tja> I'm tired.
17:45:26 <kc5tja> And I'm searching for alternative sources of income.
17:46:12 <kc5tja> I'm wondering if anyone here knows a friend who knows a friend, or better, who is interested in purchasing some volumes of stack CPUs for homebrew/hobby/production projects.
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17:50:21 * kc5tja just wants to start making some money doing something I enjoy, instead of cleaning trash, changing money at counter windows, and washing dishes all day.
17:50:40 <kc5tja> When I get home, I'm just so wiped, that homework doesn't get done, and household chores stack up.  :(
17:50:47 <kc5tja> I'm very burnt out.
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18:18:46 <arke> kc5tja!!
18:19:03 <arke> kc5tja: can you define "not" in terms of and and xor for me?
18:19:10 <arke> and and inclusive or, i mean
18:20:52 <arke> : and 2dup or rot xor xor ;
18:21:07 <arke> : or 2dup xor rot and xor ;
18:21:43 <kc5tja> Which not?
18:21:58 <arke> : xor 2dup or rot and not and ;
18:22:00 <arke> bitwise
18:22:05 <arke> 010101 --
18:22:09 <arke> 0101 --> 1010
18:22:11 <arke> etc.
18:22:16 <kc5tja> No; negation operator is a critical component of constructing more complex logic.
18:22:31 <arke> i can define and and or without it
18:22:36 <arke> but i need it for xor
18:22:47 <arke> how do CPU's do a not?
18:22:47 <kc5tja> The basic building block for complex logic is the NAND or NOR gates; these are the same as AND and OR, but they have inverters at the output.
18:23:00 <arke> ok
18:23:02 <kc5tja> They XOR it or NAND it with all ones.
18:23:26 <arke> how do they implement an inverter nowadays? i know how they did it with relays...
18:23:28 <kc5tja> Note that you can make an AND gate from two NAND gates, but you CANNOT do the reverse. :)
18:23:35 <kc5tja> Transistors.
18:23:43 <arke> lol
18:23:48 <arke> there lies my problem
18:23:49 <arke> how
18:23:50 <arke> lol
18:23:59 <kc5tja> If the input signal is high, the N-type transistor turns on, bringing the output low.
18:24:00 <arke> ive been trying to figure it out in school all day
18:24:13 <kc5tja> If the input signal is low, the P-type transistor turns on, bringing the output high.
18:24:30 <kc5tja> The N-type transistor is connected to ground.
18:24:33 * arke punches self
18:24:36 <arke> duh
18:24:37 <kc5tja> The P-type transistor is connected to +Vdd.
18:24:38 <arke> lol
18:24:56 <arke> er
18:24:56 <arke> wait
18:25:04 <arke> is this pno or npn youre talking about?
18:25:07 <arke> pnp*
18:25:08 <kc5tja> MOS
18:25:13 <arke> eep!
18:25:14 <arke> ??
18:25:40 <kc5tja> Metal Oxide Semiconductor is what it stands for.  I'm sure you've heard the term "CMOS" before?  Complimentary MOS technology is what it stands for.
18:26:26 <kc5tja> Basically, if your gates are built exclusively out of N-type and a P-type MOS transistors, you're using CMOS logic.
18:26:45 <kc5tja> TTL and ECL uses bipolar transistors (usually just NPN transistors)
18:27:08 <kc5tja> They're moderately fast, but they're bigger on the chip, and draw more power.
18:27:18 <arke> :)
18:27:39 <kc5tja> Besides, highly integrated CMOS is actually faster now-a-days than TTL or ECL is.
18:27:42 * arke is making a little CPU-emulating thing
18:27:46 <arke> as in, the actual thing
18:27:54 <arke> you dont have to worry about alot
18:28:08 * kc5tja nods
18:28:15 <kc5tja> You're emulating it at the logic gate level?  :)
18:28:19 <arke> yep
18:28:29 <arke> the base unit here is teh transistor
18:28:42 <kc5tja> You're emulating TTL?!  :)
18:28:47 <arke> which has 3 things: in, out, power
18:28:58 <kc5tja> Well, not exactly.  :)
18:29:12 <kc5tja> I'd say that's true for an inverter.
18:29:13 <kc5tja> :)
18:29:14 <arke> (this is probably wrong compared to the real thing, but it works, and it prolly relates to the real thing alot)
18:29:40 <kc5tja> What kind of technology are you making the emulator for?  NPN transistors or MOS transistors?
18:30:00 <arke> well, kinda neither lol
18:30:12 <kc5tja> I see.  :)
18:30:21 <arke> i dont know that much about it, really. i studied it a little.
18:30:26 * kc5tja nods
18:30:52 <arke> basically, each tran gets 2 args and returns one
18:30:52 <arke> lol
18:31:14 <arke> its likely to be structured that way, i havent completely decided yet
18:31:32 <kc5tja> The problem with a transistor used in this fashion is, it's a switch.
18:31:46 <kc5tja> Therefore, as a switch, it's either conducting or it's not.
18:31:47 <arke> pretty much
18:32:06 <arke> pretty much
18:32:14 <kc5tja> The output of a logic gate needs to alternately be connected to ground or to +Vdd/+Vcc (there are exceptions to this when dealing with I/O devices; but for now....)
18:32:29 <kc5tja> Thus, the output of each gate, including an inverter, needs at least two transistors.
18:32:42 <kc5tja> One that connects to GND, the other to +V.
18:32:43 <kc5tja> :)
18:33:07 <arke> i imagine AND-BIT to be a simple tran(a, b)
18:33:12 <kc5tja> This is why a CMOS inverter has two transistors: the P- and N-type transistors are switches that conduct in such a manner to effectively invert the input to its output.
18:33:21 <kc5tja> Explain your notation please?
18:33:56 <arke> basically, a and b are n and p, and it "returns" the other n
18:33:58 <arke> sorta
18:33:58 <arke> lol
18:34:10 <kc5tja> No
18:34:12 <kc5tja> :)
18:34:17 <arke> i know its not like that
18:34:22 <arke> but im trying to make it semi-simple
18:34:46 <arke> its prolly like tran(tran(a,p),tran(b,p)) or such
18:34:46 <arke> :)
18:35:20 <kc5tja> Well, that's certainly closer.
18:35:42 <arke> :)
18:36:40 <arke> im not sure how to implement that
18:36:46 <arke> lol
18:39:21 <arke> even simple things like tran(not(tran(tran(a,p),tran(b,p))),tran(a,p)+tran(b,p)) could get hairy quite fast
18:39:30 <arke> (ill let you guess what that is
18:39:34 <arke> lol
18:39:38 <arke> or what i hope it is
18:39:58 <kc5tja> What is +?
18:40:22 <arke> combinator
18:40:25 <kc5tja> I can't tell from this what it is.
18:40:33 <kc5tja> That doesn't tell me anything.  :)
18:40:33 <arke> just puts them together
18:40:39 <kc5tja> So, it's a wire-tie.
18:40:39 <arke> and im hoping its xor :)
18:40:43 <arke> yes.
18:41:02 <kc5tja> XOR is (A & !B) | (!A & B)
18:41:21 <kc5tja> XNOR is (A & B) | (!A & !B)
18:41:42 <kc5tja> So the above might just need an extra inversion stage to make it an XOR gate.
18:41:48 <kc5tja> I'm guessing.
18:42:49 <kc5tja> Oh well.  I'm going to take a small nap.  I'm wiped.
18:43:06 <kc5tja> Plus, I need to sit down and really think about hwo I'm going to make extra income.  :/
18:43:07 <arke> ok :)
18:43:12 <arke> :(
18:43:13 <arke> later
18:43:17 * arke watches TV
18:43:17 * kc5tja does not want to work for In-N-Out forever... 
18:43:20 <arke> lol
18:43:27 * arke doesnt wanna work for mcd forever
18:43:32 <arke> get a job coding forth!
18:45:37 <kc5tja> I'd love to.
18:45:46 <kc5tja> Care to elucidate on how I'm to go about doing this?
18:55:19 <arke> ask i440r
18:55:20 <arke> :)
19:01:52 <arke> i need to figure out how to use gforth.
19:15:47 * MysticOne beats kc5tja animal style!
19:20:13 * arke beats MysticOne just for the hell of it
19:20:20 * MysticOne takes it like a man
19:25:24 * arke takes a broomstick and ...... let your imagination fill the rest
19:27:05 * MysticOne watches arke sweep the floor
19:27:40 <arke> lol
19:33:18 <kc5tja> ???
19:33:31 <arke> :)
19:33:31 <kc5tja> HAHA!  NICE comeback!! :D
19:33:39 <MysticOne> hehe
19:33:55 * kc5tja just downloaded a hacked version of PacMan for the Atari 2600.  It's neat because it's MUCH more accurate to the original arcade game than the 2600's first version of PacMan.
19:34:30 <arke> :)
19:34:45 <arke> i need to choose a lang.
19:34:49 <arke> forth? C? SML?
19:34:54 <arke> so many choices...
19:36:58 <arke> brb, dinner
21:25:53 <arke> back :)
21:25:58 <arke> what did I miss?
21:26:00 <arke> ...
21:26:03 <arke> nothing, huh?
21:31:56 <kc5tja> Nothing at all.
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21:35:39 <Sonarman> hi skylan 
21:37:57 <arke> kc5tja: what lang?
21:37:57 <arke> kc5tja: eck
21:37:57 <arke> kc5tja: can you help me get gforth figured out?
21:41:08 <kc5tja> Probably the best thing to do to learn GForth is to follow a ANSI Forth tutorial.
21:41:23 <kc5tja> GForth is pretty much a verbatim implementation of ANSI Forth.
21:43:28 <skylan> Hello Sonarman
21:43:39 <arke> hrm
21:43:45 <arke> kc5tja: how do CPU clocks work?
21:44:29 <kc5tja> That depends on the CPU.
21:44:35 <arke> well
21:44:47 <kc5tja> But the clock is just a monotonic pulse train -- it sets the pace with which the CPU gets things done.
21:44:50 <arke> choose any one you can describe well
21:44:59 <arke> ok
21:45:02 <kc5tja> OK, I'll choose the 6502 because it's so easy.
21:45:04 <arke> how is it interfaced?
21:45:26 <kc5tja> You just supply a square wave to the clock input.
21:45:46 <arke> er
21:46:01 <kc5tja> On the 6502, when the clock is low, the CPU places the next memory address to read or write from on the address bus.  It also supplies the read/write bus command, and sets up other critical signals.
21:47:09 <kc5tja> When the clock is high, nothing actually changes on the bus, because the high-phase (so-called "phase 2" in 6502 parlance, since it's the second bus phase) is just a slice of time used to let the addressed memory settle on its new contents.
21:47:29 <kc5tja> When the clock goes from high to low, the 6502 knows that the previous bus transaction is done, and it can advance to the next.
21:47:34 <kc5tja> At the same time...
21:48:05 <kc5tja> When the clock goes low, it advances to the next CPU state, which could be "fetch another instruction," or it could be part of an instruction previously fetched.
21:48:33 <kc5tja> OK, it's harder to explain than I predicted.
21:49:31 <arke> er,,,
21:56:51 * warp0x00 dances
21:57:19 <arke> oh
21:58:00 <arke> kc5tja: you mean it sends signal 1, at which time teh bus is loaded, and then signal 2, at which time teh instruction is executed, and then signal 1 again, etc. ???
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22:09:48 <arke> y0 Serg_Penguin ]
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22:12:33 <Serg_Penguin> hi
22:13:33 <Serg_Penguin> yesterday i was attempting to buy old Soviet reproduction table for 50$, new imported now is 400$
22:13:51 <Serg_Penguin> but the one was damaged and some parts lost
22:14:22 <Serg_Penguin> now i'll get photo-enlarger even cheaper - to move cam up and down over table
22:14:30 <Serg_Penguin> brb
22:17:59 <kc5tja> arke: No, the clock controls when the CPU does various things.
22:18:15 <kc5tja> arke: The CPU doesn't generate the clock; the clock is an input to the CPU.
22:18:49 <arke> thats what i meant :)
22:19:07 <kc5tja> Also, the CPU is doing many things all at the same time.
22:19:40 <kc5tja> The 6502 has several buses inside it, so that it can move more than one byte of data between registers per clock cycle.
22:20:21 <kc5tja> Anyway, I have school tomorrow.
22:20:23 <arke> what would be teh best way for me to implement some sort of clock?
22:20:25 <kc5tja> I need to get to bed.
22:20:34 <kc5tja> arke: I can't answer that question.
22:20:44 <arke> hrm
22:20:44 <arke> ok
22:20:45 <arke> :)
22:20:54 <kc5tja> okies
22:20:55 <arke> kc5tja: one last question ---- how old are you? :)
22:20:59 <kc5tja> Sorry I couldn't help much.
22:21:06 <kc5tja> 28.  Feb 24, I'll be 29.  :)
22:21:10 <arke> you helped much more than you might think uou did :)
22:21:12 <arke> :)
22:21:36 <kc5tja> OK, I'm off to bed.
22:21:42 <arke> night :)
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