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12:23:52 <futhin> sexy
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20:01:29 <futhin> hi
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21:30:17 <Speuler> g'd morning
21:31:33 <oxygene> good morning
21:31:39 <Speuler> hsa anyone heard of a forth written in brainfuck ?
21:31:43 <Speuler> has ...
21:32:49 <Speuler> would make for an extremely portable interpreter base ...
21:45:48 <I440r___> hi
21:45:57 <I440r___> hehe
21:46:14 <oxygene> lol
21:46:30 <oxygene> is there a brainfuck-compiler? ;)
21:46:38 <I440r___> it would be IMPOSSIBLE to code
21:46:50 <I440r___> brain is purlely linear code
21:46:50 <I440r___> no functions
21:46:59 <I440r___> orrather
21:46:59 <I440r___> ONE function heh
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21:50:59 <oxygene> I440r___: hmm... isn't brainfuck turing complete? so it should be possible somehow... ;)
21:51:15 <oxygene> otoh there are a lot turing mini-languages ;)
21:51:44 <Speuler> I440r___: nope. BF knows iteration
21:54:47 <Speuler> oxygene: i doubt there is a "real" compiler. there should be translators, and pseudo-compiler which pack a BF interpreter with the source
21:55:21 <Speuler> there is a brainfuck interpreter, written in brainfuck
21:56:39 <Speuler> I440r___:   bf uses   [  and   ]  as loop contruct
21:56:46 <Speuler> struct...
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22:10:57 <I440r___> yea
22:11:03 <I440r___> i know
22:11:07 <I440r___> but u cant call a function in it
22:11:33 <I440r___> would be good if u could 
22:11:46 <Speuler_> not directly ... have to implement it
22:12:35 <I440r___> would have to be like assembler labels
22:13:03 <Speuler_> through conditional loop, and update of the content of cell pointer points to
22:14:22 <Speuler_> a few cells encode in bin the function number. these cells are used by [ ] to skip/branch to the corresponding function
22:15:01 <I440r___> but theres no stack
22:15:05 <Speuler_> there is
22:15:12 <I440r___> so you can to call xyzzy return
22:15:14 <Speuler_> it is called "the pointer"
22:15:17 <I440r___> and call xyzzy later and return 
22:15:33 <I440r___> yea
22:15:42 <I440r___> and "the pointer" can only point to ONE location
22:15:50 <I440r___> so it would need to POINT to a SP location
22:15:54 <Speuler_> two stacks:  inc / dec n times "the pointer" to point to one or other stack :)
22:15:57 <I440r___> and then be pointed to an RP location
22:15:57 <I440r___> etc
22:16:05 <I440r___> with SP and RP being updated 
22:16:42 <I440r___> you could have 0000 = IP
22:16:48 <I440r___> 0002 = SP
22:16:53 <I440r___> 0004 = RP
22:17:06 <I440r___> can you store immediate values in the pointer ?
22:17:41 <Speuler_> where would the immediate value come from ?
22:18:02 <I440r___> mov 0000 pointer
22:18:02 <I440r___> pointer NOW points to IP
22:18:16 <I440r___> just being able to back the pointer up
22:18:22 <I440r___> and move it rorward
22:18:25 <Speuler_> nop, but you can inc/dec the pointer
22:18:26 <I440r___> and increment and decrekent the contents of where it points
22:18:30 <I440r___> is next to useless
22:18:34 <I440r___> ugh
22:18:41 <I440r___> so you have ONE pointer
22:18:41 <Speuler_> do it often enough, and it is like having loaded with value
22:18:46 <I440r___> that acts as IP, SP nd RP
22:18:50 <I440r___> cant be done
22:20:38 <Speuler_> guess i'd try nest,unnest,next before doing any primitives 
22:20:47 <I440r___> need to be able to store ANY value at ANY location
22:20:52 <I440r___> not just advance pointer
22:20:57 <I440r___> reverse pointer
22:20:59 <Speuler_> you can
22:21:01 <I440r___> increment where pointer points to
22:21:05 <I440r___> etc
22:21:06 <Speuler_> only iteratively
22:21:20 <I440r___> itterativly CANT work heh
22:21:24 <I440r___> you NEED function calls
22:21:29 <I440r___> immediate fetches and stores
22:21:33 <Speuler_> build them
22:21:37 <Speuler_> build them too
22:21:37 <I440r___> brainfuck is next to useuelss
22:21:45 <I440r___> you can do ANY ONE funciton in brainfuck
22:21:50 <I440r___> you couldnt do anything usefull
22:22:32 <Speuler_> like, an x86 emulator :)
22:23:13 <I440r___> heh
22:23:40 <Speuler_> with "standard" bf, impossible
22:23:56 <Speuler_> uses max 30000 cells
22:24:06 <Speuler_> needs xbf
22:24:16 <Speuler_> extended brainfuck
22:24:22 <I440r___> heh
22:24:27 <Speuler_> 10 million cells
22:24:38 <Speuler_> but, you can implement an AND gate
22:24:54 <Speuler_> and logically connect ins and out
22:25:16 <Speuler_> so you implement a cpu
22:25:27 <Speuler_> from nands
22:25:45 <Speuler_> from bf implemented nands
22:27:07 <Speuler_> if bf is turing complete, a 2-instruction language would do too
22:27:10 <I440r___> heh
22:27:22 <I440r___> you could prolly do ONW nand gate :P
22:27:22 <I440r___> one
22:27:39 <Speuler_> "shift" and "fuse"
22:27:51 <Speuler_> or "step" and "fuse"
22:28:03 <Speuler_> the program would look like:
22:28:20 <Speuler_> step step fuse step fuse fuse step fuse step step step fuse ...
22:29:00 <I440r___> ?
22:30:06 <Speuler_> the step/fuse interpreter is an array of nands, and a connection matrix
22:31:03 <I440r___> what does step do
22:31:12 <I440r___> what does fuse do
22:31:25 <Speuler_> advance to the next connection point of the matrix
22:31:34 <Speuler_> w/o fuse
22:32:12 <Speuler_> fuse connects
22:32:21 <Speuler_> and advances to the next point
22:32:42 <I440r___> u lost me
22:32:46 <I440r___> totally
22:32:46 <I440r___> heh
22:33:05 <Speuler_> t'is like a breadboard
22:33:33 <Speuler_> ehm
22:33:35 <Speuler_> not quite
22:35:26 <Speuler_> column n: outputs of nand n
22:35:44 <Speuler_> row 2n: input 1 of nand n
22:35:51 <Speuler_> row 2n+1: input 2 of nand n
22:36:28 <I440r___> each nand has how amny inputs
22:36:28 <I440r___> all would have to be teh same
22:36:34 <Speuler_> stock output of any nand on input of any nand, by fusing the corresponding point in the matrix
22:37:08 <I440r___> how would u remember what inputs and outputs were connect ed to what inputs and what outputs heh
22:37:35 <Speuler_> the program source tells me
22:37:42 <Speuler_> no need to remember :)
22:38:03 <Speuler_> oh.
22:38:13 <Speuler_> i put a matrix in mem, and store bits in it
22:38:50 <Speuler_> that is, i compile the source to object ...
22:39:09 <Speuler_> translate "fuse" into 1
22:41:32 <Speuler_> stepping beyond last matrix point starts the program (the resulting gate logic)
22:42:09 <Speuler_> i need a fuse point for 1 and 0 too.
22:42:42 <Speuler_> either 1 or 0
22:43:33 <Speuler_> no need
22:44:23 <Speuler_> i pull up open inputs in the emulated nands
22:45:23 <Speuler_> output of unconnected nand is 0
22:45:28 <I440r___> will be very complex
22:45:31 <I440r___> and slow heh
22:45:39 <Speuler_> can invert that for zero
22:45:48 <Speuler_> eh, 1
22:46:21 <Speuler_> can be ported to hardware easily
22:46:36 <Speuler_> where it will be quick
22:47:33 <I440r___> i had a fone interview today
22:47:40 <I440r___> with flir
22:47:52 <I440r___> they make infared imaging stuff
22:47:54 <Speuler_> i preferred a chicken
22:48:00 <I440r___> milatary use etc
22:48:02 <I440r___> and police 
22:48:14 <Speuler_> ah
22:48:18 <I440r___> ?
22:48:49 <Speuler_> nasty stuff that
22:48:59 <I440r___> what is
22:49:23 <Speuler_> equip with military potential
22:49:57 <I440r___> oh hehe
22:50:06 <Speuler_> was declining a job once
22:50:33 <I440r___> cant afford to decline ANY job
22:50:41 <Speuler_> (probably wouldn't have received clearance anyway:)
23:09:14 <Speuler_> :dup
23:09:14 <Speuler_> >off>off<<[->+>+<<]>>[-<<+>>]< 
23:09:25 <Speuler_> :swap
23:09:25 <Speuler_> >off<[->+<]<[->+<]>>[-<<+>>]<
23:09:59 <Speuler_> :off
23:09:59 <Speuler_> [-]
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