#+TITLE: New year, new SoC and new gateway!
#+AUTHOR: arpunk 
#+DATE: <2026-01-19 Mon>
#+OPTIONS: toc:nil
#+filetags: :work:

I've been working with a friend[fn:01] to get a second version of the
gateway prototype we made a few years ago[fn:02].  This time we aim
for a little freedom and without the design restraints we had at the
time.
 
We set our goals for a faster device, aiming for better multiple
protocol stacks in parallel, real buffering/backpressure and PCIe.
 
The first prototype ran on a Cortex‑A8 with 512 MB of RAM, USB2 and
10/100 NIC, which enabled us to boot multiple kernels –including
sel4‑based ones– with ease but runs short of resources and its getting
hard to get a hold of those old BBB.

After some delays and life stuff we managed to find some time to work
on the upgrades we had on our wishlist:
 
  - CM5 by default; Cortex‑A76 × 4
  - Real PCIe
  - M.2 slot

This new base provided us with a better expansion path.  The first
version included a built‑in ESP32C3 for Wi‑Fi/BT custom operations,
which limited the way we interacted with other devices in the mesh,
however now we can switch radios and let the firmware deal with it.

We use it at work in order to connect to remote bridges –ESP32
microcontrollers– and process information at edge before sinking the
data on premises, providing for faster data processing by decoding
payloads within the gateway with a version of Lua[fn:03] for
BEAM-based systems.

Happy new year!

* References

[fn:01] Electrolama: https://electrolama.com
[fn:02] From Concept to Hardware: https://youtube.com/watch?v=Cs6Qc0F_0rE
[fn:03] Lua in Erlang: https://luerl.org